No, I mean if you take a look at this: "DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte)" where are they getting the number of bits transferred? Is that per chip, per module, both, and then if the transfer of the chip does not meet the module, how do they combined those rates to get 64 bits? my guess is since there are 16 chips, each cheap does 4 bits/cycle, is this correct?