PCI crossfire issues?

Ah, welcome to the world of Intel.

A couple of years back Intel began the process of completely integrating the North Bridge into the CPU package itself. This started with the DRAM controller (Nehalem), IGP and PCI-Express controllers (Westmere), and finally integrating them all into one single die (Sandybridge).

With the North Bridge being completely integrated into the CPU itself, the CPU could be attached directly to the South Bridge (officially named PCH, or Platform Controller Hub) via a modified PCI-Express 2.0 link called DMI.

The Intel PCH itself provides 8 additional PCI-Express 2.0 links which are used by the motherboard manufacturer to attach add-in chips such as additional storage controllers, USB controllers, Ethernet controllers, and Audio controllers. Several of these links are made available in slot form for the user to attach whatever he or she desires, usually as 1 or 2 PCIe 1x slots, and either a PCIe 4x slot or a PCIe 16x slot running in 4x mode.

This is what trips a lot of people up. The PCIe protocol autonegotiates its own link speed between the host and the device. They can negotiate 1x, 4x, 8x, and 16x based on the number of connected sense pins. Believe it or not, if you're careful enough, you can take a high end graphics card, and cut the pins down such that it will fit in a 1x slot and it will run at 1x speed (provided that it can still get enough power). Furthermore, you can take a high end graphics card, cover the appropriate pins in scotch tape, and put it into a full 16x slot and it will run at a lower speed.

Now, Intel's most recent microprocessors provide either 16 PCIe lanes (LGA1156/LGA1155/LGA1150) or 40 PCIe lanes (LGA2011) directly from the CPU itself. On Westmere and Sandybridge these lanes can be configured as either as one 16x, or two 8x. On Ivybridge they can be configured as one 16x, two 8x, or one 8x and two 4x. Sandybridge-E and Ivybridge-E provide too many configurations to list easily, so I'll leave those out.

These PCIe lanes that are connected directly to the CPU itself are really, really fast. They also have very low latency and do not interfere with other busses aside from the system memory bus.

The PCIe lanes that are connected to the PCH are quite a bit slower, and must traverse the DMI bus between the PCH and the CPU before accessing the system memory. This results in higher latency, lower throughput, and competition for bandwidth on the DMI bus that is shared by other devices. NVidia does not allow for a motherboard to be SLI certified if it would require that the user use the PCIe lanes from the PCH, they must be from the North Bridge (AMD only now) or CPU only. AMD is a bit more forgiving and does allow for a motherboard to be Crossfire certified in this instance. Crossfire will work on your board, but it will not work as well as it would were both of the slots connected directly to the CPU.

I hope that this answers your question.