using pcpartpicker to choose ram. What it all means..

The speed rating, often marketed as DDR3-XXXX or PC3-XXXXX is the maximum theoretical transfer rate of the module.

DDR3-XXXX is the IO rate per pin measured in megabits per second, and PC3-XXXXX is the IO rate per standard 64 bit memory channel measured in megabytes per second. They measure the exact same thing, one is simply 8 times larger than the other (64 IO pins per x86 memory channel divided by 8 bits per byte).

A higher transfer rating is better but higher transfer ratings also put more stress on the memory controller. Really high speed modules require additional tweaking on part of the user. In general, DDR3-1600 is a safe bet if you don't feel like tweaking your computer or diagnosing crashes..

CAS latency refers to column address strobe. It is the time between the memory controller sending a DRAM column address on the DRAM address bus and the data at that row/column intersection being stable on the IO bus. Despite being categorized as "random access memory" SDRAM or Synchronous Dynamic Random Access Memory is not actually random in the same sense as SRAM or Static Random Access Memory.

SRAM is organized and addressed linearly, with a constant real time delay between accesses regardless of where the target address is located. CPU cache is of SRAM design.

DRAM is organized into rows and columns in a fashion very similar to a spreadsheet. A typical modern DRAM chip consists of a number of banks on a chip (typically four, but up to eight can be addressed) each of which can be active and operating independently. The memory controller selects the bank that it wants, sends a row address, waits for the row to charge, and then sends column addresses in rapid succession. So, in order to read from or write to a truly random address the DRAM controller must first select the bank that the address is located in, close the open row, send the destination row address, open and sense the destination row, and then send the relevant column address. On an individual bank basis you can imagine that this process actually takes quite a bit of time.

Fortunately memory access patterns are rarely ever truly random. Most memory patterns are spatially related, so successive memory accesses are very likely to be to the same column that's already open. This is why CAS is generally regarded as the most important memory timing value; DDR3 allows for up to eight sequential column addresses to be read or written in rapid succession. The memory controller can still keep the memory rank busy (any combination of DRAM chips that form a 64 bit IO bus is called a rank) by issuing operations to another bank while waiting for the column data to respond. Thus, it's possible for a strong memory controller to keep a high speed memory module busy 100% of the time even if the memory has a high CAS latency, but a low CAS latency makes it easier for every component involved.

Dual channel, and by extension triple and quad channel, operate two separate 64 bit IO buses in parallel. These do not have to be strictly identical but they do have to run at the same speed and with the same timings so it is best to buy a set of modules that have been tested to play nice together in such a configuration.

I hope that this answered your question.