AnEwG :
I hear this a lot: Real Hex or quad core processors. Does that mean that the 4300, 6300 don't actually have the number of cores signified? If that is such the case then what would be a Real quad or hex core?
Beh, you just opened up a can of worms!
"real" is a qualifier that unknowledgeable fanboys love to tack on to a product that they love in order to better validate it against its competition.
Microprocessor engineers have a huge amount of leeway in how they arrange and present the hardware that they are designing. Most of the time this results in dramatically different designs that are wholly incompatible, such as MIPS vs ARM. However, different generations of the same design often require a bit more finesse to examine.
For example, x86 microprocessors (all of them dating back to the Pentium anyway) have an instruction called CPUID. This instruction is used to set the state of the machine such that the model and capabilities of the microprocessor can be identified. Prior to this there was no explicit way to tell the difference between an 80486 and an 80386, or any of their predecessors; they all feature full backward compatibility so engineers had to write often unreliable heuristic routines in order to exploit differing behaviour in order to tell them apart. The reason for this is that while different generations of CPUs are different internally, they present themselves in a nearly identical fashion and software doesn't care.
Presentation is as important in hardware as it is in software. This is what trips a lot of people up, presentation masks implementation. A "core" is not a concretely defined term. At best it can be loosely described as a discrete state tracking device. When talking about a device that performs arbitrary operations defined within an Instruction Set Architecture the definition expands a little bit. When that ISA is further narrowed to the IA32 instruction set and associated ISA extensions the presentation is that of a logical processor implementing the IA32 instruction set with associated ISA extensions. The implementation of that logical processor (as a physical core) is still entirely up to the designer.
Although AMD and Intel both present their micro architectures in the same fashion (there are only minor logical differences) there are many, many physical differences between them. Many people assume that the brand new Haswell microarchitecture (4th Gen Core i7) is a descendant to the Ivybridge microarchitecture (3rd Gen Core i7) , which is a descendant of Sandybridge (2nd Gen Core i7), which is a descendant of Westmere (1.5 gen Core i7), which is a descendant of Nehalem (1st Gen Core i7), which is a descendant of Penryn (2nd Gen Core 2), which is a descendant of Conroe (1st Gen Core 2) which is a descendant of Prescott (3rd Gen Pentium 4). Wait, that's wrong... Conroe (Core 2, released in 2006) is a descendant of Yonah (1st Gen Core) which was a mobile-only microprocessor that is itself a descendant of the Pentium 3 (released in 1999) which is a member of the P6 family of microarchitectures. All 3 major revisions of the Pentium 4 micro architecture (collectively known as NetBurst) are a massive departure from anything that came before them, and nothing came after them in an evolutionary fashion. Thanks to architectural differences, a 2.3Ghz Core 2 Duo microprocessor could outperform a 3.5Ghz dual-core Pentium. In some cases a single core Core 2 Solo could outperform a dual-core pentium. Don't let core count fool you; cores are easy to reproduce, but the architecture of the core itself is hard to develop!.
Lets link this concept of implementation and presentation together. At a bare minimum 4 building blocks are needed to make an ISA core work: an data source (typically exposed to the cores as an instruction cache and a data cache), a front end (instruction decoding, state tracking, register sets), a back end (integer execution, floating point execution, logic execution, address generation, memory access), and control logic (makes everything work together nicely).
Each designer is free to take liberties with these as much as they want as long as the end result is logically equivalent to that expected by the instruction set.
Starting with the first generation Core i7 microprocessors (Nehalem) Intel has decided to use fully discrete cores. Each core has its own L1 instruction cache, its own L1 data cache, its own L2 cache, its own back end, and
two front ends. The backend of Intel's microarchitecture is powerful enough to serve two front-ends, each of which is presented to the operating system as a logical processor that execute the IA32 instruction set. This is the meat of Hyperthreading. All cores share an L3 cache and interconnect to the rest of the microprocessor.
AMD has decided to use non-discrete cores. Each core has its own L1 data cache, its own front end, and a partial backend (Integer, logic, address, and memory). Each core shares the rest of the backend (floating point), the L1 instruction cache, and the L2 cache with one other core. Together these are presented to the operating system as a pair of logical processors that execute the IA32 instruction set. These core-pairs can be duplicated with ease to create 4,6, and 8 core microprocessors.
So, keeping the above two designs in mind, what if a designer wants to create a 12 or 16 core microprocessor?
Lets look at some competing claims.
Intel claimed to have the first quad core microprocessor in late 2006 with the Core 2 Quad microprocessor.
AMD claimed to have the first native quad core microprocessor in 2007 with the Phenom line of microprocessors.
These are both true statements.
The difference is that Intel's Core 2 Quad microprocessor is actually a pair of Core 2 Duo microprocessors glued together on a Multi-Chip-Module whereas AMD's Phenom was a microprocessor with all four cores on a single silicon die. Despite not being a "true" or "real" quad core microproessor, the Core 2 Quad crushed the Phenom in every single benchmark. Marketing departments suck.
Intel's 8 core server CPUs are native 8 core microprocessors with all components on a single die. I'm not certain what approach they will use to create the upcoming 12 and 15 core microprocessors but AMD's 12 and 16 core server CPUs are in fact a pair of 6 and 8 core CPUs glued together on an MCM just like the Core 2 Quad.
The takeaway from this mess is that the strength of a CPU has to be assessed on its own merits, not on the clock frequency, number of cores, or whether or not the cores are "native" or "real".