I dunno wether i was happy or not to see this answer
I think i am.. Im just about to get a new board and saw my gpu is pci-e 3.0 ready.. i was recommended a M/B by a user on here... JJs0891.. but when i saw specs and then saw my gpu box, i thought i'd quickly check for some pci-e 3.0 M/B's... with little luck.. all reviews seem to say in a few years it will be everywhere but not needed right now.. but then i read pci-e 4.0 will be coming out too xD..
I ended up on wiki (yes, i know its not all true on that site, but... ) i found this techie info (of which i know little about).. the doubling of bandwidth sounds great... but with release dates of 2010.. and no signs of full compatabilty yet just seems like too long
so im in no rush for it..
full post here -
http://en.wikipedia.org/wiki/PCI_Express
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second (GT/s), and that it would be backward compatible with existing PCIe implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until 2011. New features for the PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.
PCIe 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the overhead to approximately 1.54% ((130–128)/130), as opposed to the 20% overhead of PCIe 2.0. This is achieved by a technique called "scrambling" that applies a known binary polynomial to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial.
PCIe 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, practically doubling the lane bandwidth relative to PCIe 2.0.
On November 18, 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.
PCI Express 3.1 is scheduled to be released in late 2013 or early 2014, making various tweaks to the published standard.
PCI Express 4.0
On November 29, 2011, PCI-SIG announced PCI Express 4.0 featuring 16 GT/s, still based on copper technology. Additionally, active and idle power optimizations are to be investigated. Final specifications are expected to be released in 2014 or 2015.