800mhz ram,what memclock setting in bios?

DRAM multiplier and DRAM divider are the same thing in this sense. The clock is generated by a PLL which contains at least one multiplier and at least one divider by design.

The clock source is either a crystal oscillator or an electrical oscillator. This generates a fixed frequency sinusoid (common frequencies are 25Mhz, 50Mhz, and 100Mhz) which is then passed into a trigger which turns it into a square wave, which is then passed into a buffer which reduces jitter and provides additional current drive capabilities. The output from the buffer is then fed into a programmable PLL which is responsible for generating the various system clocks. One of these clock signals will be used for the PLL's internal feedback, and it's common practice to use this same clock as a basis for the other clocks, which allows the oscillator source to be hidden. The reference clock may be 266Mhz to drive the FSB on an Intel P45 motherboard. The FSB itself transfers data four times per clock cycle (called quad pumped or QDR, conceptually very similar to DDR) giving an effective transfer rate of 1066MT/s (mega transfers per second).

The DRAM clock, which comes from the same PLL, is typically expressed as some ratio of the FSB clock. If a fixed ratio is used, all sorts of compatibility nastiness can occur. Lets look at some examples.

Take for instance a DDR2-800 module discussed above. DDR stands for double data rate which means that data is transferred on the DRAM IC's IO pins on both the rising and falling edge of the DRAM IO bus clock. Ergo, DDR2-800 uses a bus clock of 400Mhz in order to obtain a transfer rate of 800MT/s per IO pin. By the same process, we can see that a DDR2-667 module has an IO bus clock of 333Mhz, and a DDR2-533 module has an IO bus clock of 266Mhz. In order for a DRAM module to work properly, the actual DRAM IO bus clock frequency has to match the expected DRAM IO bus clock that the manufacturers intended. If a DDR2-667 module is fed a 400Mhz clock, it will behave as if it is a DDR2-800 module, but it may not be physically capable of performing at that level.

Lets look at how this can happen. As mentioned above, the DRAM IO bus clock comes from the same place as the FSB clock, and is expressed as some factor of the FSB clock. The FSB clock doesn't change much, and is typically matched to the installed CPU (although deliberately mismatching them can make for some interesting overclocking, ala the Q6600's free overclock to 3Ghz). Assuming a 266Mhz FSB (1066MT/s), a 400Mhz DRAM clock would be achieved by multiplying 266Mhz by 1.5, or in PLL terms, 3:2. Multiplied by 3, divided by 2. If that 400Mhz DRAM module (DDR2-800) is swapped out with a 333Mhz module (DDR2-667) and the 3:2 ratio is preserved, the new module will almost certainly be unstable.

One way of bringing the new module back into stable operating conditions is to reduce the FSB clock until the DRAM clock is at the expected value. By performing the same math as before, we can see that with a 3:2 DRAM to FSB ratio, a 333Mhz DRAM clock demands a 222Mhz FSB. This will work well enough for the DRAM, but any CPU installed will be underclocked to 83% of its marketed value. If a 2.66Ghz CPU was installed and configured by multiplying the 266Mhz FSB by 10 (example, Core 2 Quad Q6700), that same CPU would now run at 2.22Ghz by multiplying the 222Mhz FSB by 10.

A better way to bring the new module back into stable operating conditions is to alter the DRAM to FSB ratio. Using the same math as before, but changing the input values, we can see that a 333Mhz DRAM clock referenced against a 266Mhz FSB can be derived through a 5:4 ratio. If a new CPU is installed that uses a 333Mhz FSB (such as a Q9650), a 333Mhz DRAM clock will be derived through a 1:1 ratio.

The takeaway here is that every time you change a reference clock, every clock that references that same clock changes with it proportionally. So, if you crank up the system bus in an attempt to overclock the CPU, you will also be changing the DRAM clock at the same time. This will absolutely introduce the kind of instability that you are seeing.

The ratios on your system seem to be hidden behind the standard module speeds. This of course assumes a fixed system bus frequency. If you see 396Mhz and are expecting 400Mhz, I do think that you are on the right track.