Tamim Dari :
I have this task to "Design a 32 x 4 memory using two 16 x 4 chips". But on Google I can't find what a 16 x 4 RAM is. I know the basics of latch, flip-flops, TTL, CMOS etc. But I can't put this together.
Where do I start?
Actually I don't understand the technology’s , Can you please give a link about the how the IC's work. And this is a exam question but professor didn't teach anything about this
The DRAM IO interface can be broken into several parts: Clock (a differential clock, clock enable, and reset), Control (chip select, write enable, output enable, row address strobe, column address strobe, data queue strobe, data mask), Address (Bank Address, and Address), and Data (DQ).
The first part of the "16 x 4" refers to the width of the IC's data bus, in this case 16 bits. SDRAM used in desktops is typically 8 bits, while SDRAM used in mobile and embedded systems is typically 16 bits. High density SDRAM used in enterprise servers is sometimes 4 bits. GDDR5 used in graphics cards is almost always 32 bits, but 16 bit variants do exist.
The second part of the "16 x 4" refers to the number of independent DRAM banks on the IC. Each DRAM bank operates independently and exists to mask the DRAM latency. The IO bus is connected to all banks through a multiplexer, and the bank is selected by asserting the Bank Address inputs. A DRAM controller can issue a command to bank 0, then issue a command to bank 1, then bank 2, and then bank 3, before coming back to bank 0 to read the result. DDR SDRAM has 4 banks, DDR2 SDRAM has either 4 or 8 banks, DDR3 has 8 banks, and DDR4/GDDR5 have 16 banks.
It is possible to concatenate the data pins from multiple DRAM ICs together to form a wider bus. For example, two 8 bit DRAM ICs (commonly used in desktop PCs) can form a 16 bit bus, or eight can form a standard 64 bit bus used in most desktops and workstations. To accomplish this, the clock, control, and address signals are sent to all chips that are tied together into what is called a "rank". The clock, control, and address lines are sent to all of the DRAM ICs that are concatenated together.
I hope that this helped.
Here is a DRAM IC datasheet from Hynix that may help further
http://www.hynix.com/datasheet/pdf/dram/H5TQ1G4(8_6)3AFP(Rev0.1).pdf
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