is Amd fx 6300 really 6 core ?
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AMD
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dafuqawew
October 6, 2014 2:46:08 AM
People always said those amd cpu are not really 8cores and 6 cores CPU.
They always said amd just put 2 module on each cores so the cores will be doubled. Is that true ? They said its hyperthreaded but hyperthreading is an intel technology only.
Intel put 4 cores 8 threads. Amd put 8 cores 8 threads/6 cores 6 threads. And some pc experts i talk to they said amd cpu is really 6 cores and 8 cores. So is that true ? Whats the fact and wheres the proof ? From the amd itself and research test. Please someone give me proof and real facts thanks !!!
They always said amd just put 2 module on each cores so the cores will be doubled. Is that true ? They said its hyperthreaded but hyperthreading is an intel technology only.
Intel put 4 cores 8 threads. Amd put 8 cores 8 threads/6 cores 6 threads. And some pc experts i talk to they said amd cpu is really 6 cores and 8 cores. So is that true ? Whats the fact and wheres the proof ? From the amd itself and research test. Please someone give me proof and real facts thanks !!!
More about : amd 6300 core
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Reply to dafuqawew
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AMD example; FX 6300 has three piledriver modules. Each module has two integer cores and one Floating Point Unit. For integer work, the 6300 is a 6 core cpu. For floating point operations, it is a 3 core cpu. All cores are physical, hardware cores.
Each Intel core has the integer core and floating point unit locked together, so an i5 quad core has 4 integer cores and 4 floating point units, acting as a quad core at all times.
An Intel core that includes hyperthreading, eg the i3, has 2 physical cores (with their floating point units), and also has 2 more 'pseudo' cores which are not physically there. They are merely threads split off the main cores to increase throughput when dealing with multithreaded software.
Each Intel core has the integer core and floating point unit locked together, so an i5 quad core has 4 integer cores and 4 floating point units, acting as a quad core at all times.
An Intel core that includes hyperthreading, eg the i3, has 2 physical cores (with their floating point units), and also has 2 more 'pseudo' cores which are not physically there. They are merely threads split off the main cores to increase throughput when dealing with multithreaded software.
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Reply to sapperastro
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Like Sakkura said, the FX-6300 has six integer cores across three FPUs (floating points units). Each core needs an FPU to operate, so core count on its own is irrelevant. You could build a processor with 500 cores, but if it only has two FPUs then only two of those cores will actually be used.
AMD say that the FX-6300 has six cores, and it does. What they don't tell you is that not all six can be utilised simultaneously.
AMD say that the FX-6300 has six cores, and it does. What they don't tell you is that not all six can be utilised simultaneously.
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Reply to bicycle_repair_man
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Reply to sapperastro
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dafuqawew
October 7, 2014 6:56:08 AM
Best solution
While a lot of people have mentioned the number of ALU clusters and SIMD clusters on AMDs architecture, that alone is not the biggest difference.
AMDs bulldozer, piledriver and steamroller architecture feature CMT.
In AMDs bulldozer and piledriver architecture, AMD implemented CMT by duplicating the ALU cluster.
In AMDs steamroller architecture, AMD implemented CMT by duplicating the decoders AND the ALU cluster.
AMD calls a CMT core a "module". A module would be considered a physical core.
This does not necessarily mean that the FX 6300 will have the performance of a 6 core.
Because it still shares the branch predictor, fetch and decoders (in case of bulldozer and piledriver), which have known to bottleneck the backend (execution stage).
So if you pressure the frontend to much, it will starve the backend which will result in lower throughput.
AMDs bulldozer, piledriver and steamroller architecture feature CMT.
In AMDs bulldozer and piledriver architecture, AMD implemented CMT by duplicating the ALU cluster.
In AMDs steamroller architecture, AMD implemented CMT by duplicating the decoders AND the ALU cluster.
AMD calls a CMT core a "module". A module would be considered a physical core.
This does not necessarily mean that the FX 6300 will have the performance of a 6 core.
Because it still shares the branch predictor, fetch and decoders (in case of bulldozer and piledriver), which have known to bottleneck the backend (execution stage).
So if you pressure the frontend to much, it will starve the backend which will result in lower throughput.
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Reply to vmN
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Which is why Windows and Linux load cores 0,2,4 first. This makes sure the only time such pressure is ever applied is when the CPU is under very heavy loads.
So others can comprehend; FX 6300 as our example again. There are 6 cores, labelled 0,1,2,3,4,5. 0 and 1 are on one module, 2 and 3 on another, and so on.
In order to take the strain off the frontend, one core from each module is loaded first before the second core in each module is then loaded. This stops performance hits like those mentioned by vmN unless the load is maxing out all the cores. This is one reason why Bulldozer came across as horrid in the very first benchmarks released. Windows/Linux added in updates so that loads are distributed as per the above which increased performance by a substantial margin.
So others can comprehend; FX 6300 as our example again. There are 6 cores, labelled 0,1,2,3,4,5. 0 and 1 are on one module, 2 and 3 on another, and so on.
In order to take the strain off the frontend, one core from each module is loaded first before the second core in each module is then loaded. This stops performance hits like those mentioned by vmN unless the load is maxing out all the cores. This is one reason why Bulldozer came across as horrid in the very first benchmarks released. Windows/Linux added in updates so that loads are distributed as per the above which increased performance by a substantial margin.
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Reply to sapperastro
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dafuqawew
October 11, 2014 11:38:01 AM
It has 3 modules which consist of 6 integer cores and 3 floating point units. Did you even bother reading the replies you have gotten to your question?
[/quotemsg]
sorry cant understand all those technical stuff they're saying , glad you came up and explain what they are saying and those initials. thanks guys
[/quotemsg]
sorry cant understand all those technical stuff they're saying , glad you came up and explain what they are saying and those initials. thanks guys
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Reply to dafuqawew
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A modern "core," even a relatively narrow modern core like that found in a PD module, has more transistors and more execution resources than any core from 10 years ago, so by any standard that an FX-6300 isn't a 6 core CPU, we would also have to degrade the core count of any previous "single core" chips with even less execution resources to some fraction of a core.
Is a PPC G4 only 1/10th of a core then by todays standards? It's still a core, it's just a weaker core than what we have now.
Count the transistors and execution resources in a haswell core, vs a piledriver core, and you'll see why people get a bit upset over core count being used as a yardstick to measure and sell CPUs. It can be very deceiving if accompanied by a false premise that all modern cores must somehow be created equal. A Haswell core has more execution resources than a PileDriver module, but that doesn't mean that an AMD core isn't a core.
Any rational consumer should be familiar with the reality that core count is not a measure of computing performance. I have a quad core cell phone, but any one of the cores in my piledriver desktop would outmaneuver the entire quad core in my cell phone for execution performance. Does this mean my cell phone isn't really a quad core?
Is a PPC G4 only 1/10th of a core then by todays standards? It's still a core, it's just a weaker core than what we have now.
Count the transistors and execution resources in a haswell core, vs a piledriver core, and you'll see why people get a bit upset over core count being used as a yardstick to measure and sell CPUs. It can be very deceiving if accompanied by a false premise that all modern cores must somehow be created equal. A Haswell core has more execution resources than a PileDriver module, but that doesn't mean that an AMD core isn't a core.
Any rational consumer should be familiar with the reality that core count is not a measure of computing performance. I have a quad core cell phone, but any one of the cores in my piledriver desktop would outmaneuver the entire quad core in my cell phone for execution performance. Does this mean my cell phone isn't really a quad core?
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Reply to mdocod
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@mdocod
You missed the point. It is not the amount of transistors that determines the core. It only determine the size of a core.
The reason why some wont consider the FX 6300 a 6-core is because its "cores" share fundamentially component of a core.
You can break a core up in 2 groups.
The frontend and the backend.
The frontend:
The branch predictor, fetch and decode stages will be considered the frontend.
A real physical core, would not be able to function without these cores. How will the backend even get the data, or translate it from CISC instructions to RISC instructions?
The backend:
The backend is what some refer to as the execution stages.
A real core would not function without a backend, because then it would not be able to process the incoming data.
You missed the point. It is not the amount of transistors that determines the core. It only determine the size of a core.
The reason why some wont consider the FX 6300 a 6-core is because its "cores" share fundamentially component of a core.
You can break a core up in 2 groups.
The frontend and the backend.
The frontend:
The branch predictor, fetch and decode stages will be considered the frontend.
A real physical core, would not be able to function without these cores. How will the backend even get the data, or translate it from CISC instructions to RISC instructions?
The backend:
The backend is what some refer to as the execution stages.
A real core would not function without a backend, because then it would not be able to process the incoming data.
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Reply to vmN
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vmN,
I'm very familiar with CPU architecture:
One of my most used references: http://www.agner.org/optimize/microarchitecture.pdf
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There are lots of way to arrange execution engines.
By my standard, if a single thread had access to all of the execution resources (both front and and back end) in a module and the ability to completely displace another threads access to those resources, then it would be a single core with a dual threaded fetch. As it is designed, a single thread does not have access to all of the execution resources in a module. In fact, there is a hardware enforced 50/50 split of the front ends throughput when 2 threads are active on the module. If, like a haswell core (which has execution resources similar to an entire PD module and then some), the scheduler could schedule work on any execution port in the module from a single thread, then it would be a single core module, not a dual core module. Also, if, like hyperthreading, there was no hardware enforced "split" on the front-end, then again, it could not be defined as 2 cores per module.
Hyperthreading has absolutely no hardware enforced scheduling priorities, it's opportunistic and adjustments are made to priority at the software level, which means that one thread in a hyperthreaded core can effectively displace another threads access to both the front or back end of the CPU for many subsequent cycles.
In the case of the PD/BD module, the front end is ALWAYS available for both back ends in a nearly even split, there is no way for one thread to displace the entire throughput of the front end and prevent access to the other core, thus, even though the front end is shared, it is always available to decode and schedule work on both cores, thus, the front-end/back-end relationship that must be in place to fulfill the definition of a "core" by whatever standard, is fulfilled, albeit in a manner that has some shortcomings.
I'm very familiar with CPU architecture:
One of my most used references: http://www.agner.org/optimize/microarchitecture.pdf
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There are lots of way to arrange execution engines.
By my standard, if a single thread had access to all of the execution resources (both front and and back end) in a module and the ability to completely displace another threads access to those resources, then it would be a single core with a dual threaded fetch. As it is designed, a single thread does not have access to all of the execution resources in a module. In fact, there is a hardware enforced 50/50 split of the front ends throughput when 2 threads are active on the module. If, like a haswell core (which has execution resources similar to an entire PD module and then some), the scheduler could schedule work on any execution port in the module from a single thread, then it would be a single core module, not a dual core module. Also, if, like hyperthreading, there was no hardware enforced "split" on the front-end, then again, it could not be defined as 2 cores per module.
Hyperthreading has absolutely no hardware enforced scheduling priorities, it's opportunistic and adjustments are made to priority at the software level, which means that one thread in a hyperthreaded core can effectively displace another threads access to both the front or back end of the CPU for many subsequent cycles.
In the case of the PD/BD module, the front end is ALWAYS available for both back ends in a nearly even split, there is no way for one thread to displace the entire throughput of the front end and prevent access to the other core, thus, even though the front end is shared, it is always available to decode and schedule work on both cores, thus, the front-end/back-end relationship that must be in place to fulfill the definition of a "core" by whatever standard, is fulfilled, albeit in a manner that has some shortcomings.
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Reply to mdocod
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@mdocod
As you said, that is your standards.
A thread in SMT also do not have access to all ressources.
Haswell have more execution units than PD. Also performance is not only dictated by the amount of execution units, but also like prediction, prefetch, cache, uop-cache, loop-detection, latencies, how fast a miss-prediction will be discovered, and so on..
Also there is nothing like a "single core module", as that beats the purpose of a module.
A haswell core is not a module.
The instruction queue is statically split in a haswell core. So no, a single thread would not be able to gain access to all the frontends ressources.
A core is essentially a CPU. So a multi-core CPU is basically a multi-CPU CPU.
Therefore a core needs its own fundamental component to function as its own physically core.
The FX 6300 is not 6 physical cores. It is 3 physical CMT cores.
Remember that CMT is not an imlementation of CMP.
As you said, that is your standards.
A thread in SMT also do not have access to all ressources.
Haswell have more execution units than PD. Also performance is not only dictated by the amount of execution units, but also like prediction, prefetch, cache, uop-cache, loop-detection, latencies, how fast a miss-prediction will be discovered, and so on..
Also there is nothing like a "single core module", as that beats the purpose of a module.
A haswell core is not a module.
The instruction queue is statically split in a haswell core. So no, a single thread would not be able to gain access to all the frontends ressources.
A core is essentially a CPU. So a multi-core CPU is basically a multi-CPU CPU.
Therefore a core needs its own fundamental component to function as its own physically core.
The FX 6300 is not 6 physical cores. It is 3 physical CMT cores.
Remember that CMT is not an imlementation of CMP.
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Reply to vmN
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By my interpretation, a thread running on a haswell core does indeed have access to all execution resources. By "execution resources" I mean the back-end execution ports. You have a different interpretation or definition of "execution resources" than I do I suppose.
Basically, we could go around for weeks on semantics, I'm not interested in that. From my perspective, there are enough key elements in place for the "core count" to be reasonably legitimate. I'm not bothered by it.
Basically, we could go around for weeks on semantics, I'm not interested in that. From my perspective, there are enough key elements in place for the "core count" to be reasonably legitimate. I'm not bothered by it.
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Reply to mdocod
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mdocod said:
By my interpretation, a thread running on a haswell core does indeed have access to all execution resources. By "execution resources" I mean the back-end execution ports. You have a different interpretation or definition of "execution resources" than I do I suppose. Basically, we could go around for weeks on semantics, I'm not interested in that. From my perspective, there are enough key elements in place for the "core count" to be reasonably legitimate. I'm not bothered by it.
In my previous post I did not mention execution resources.
Execution is not everything about CPUs.
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Reply to vmN
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Cache is not everything about CPUs. See I can do it too.
Take that to it's ultimate conclusion, and any post I make that doesn't include a detailed description of all the thousands of intricacies in a CPU will be met with a response pointing out one of the things I must now know about CPUs. I'm not going to participate in helping you get off like that. Goodbye.
Take that to it's ultimate conclusion, and any post I make that doesn't include a detailed description of all the thousands of intricacies in a CPU will be met with a response pointing out one of the things I must now know about CPUs. I'm not going to participate in helping you get off like that. Goodbye.
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Reply to mdocod
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