How much does latency matter? Or rather can combine CL10 with CL9 or CL11

Oggi-Wan

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Jan 23, 2014
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Basically I have a DIMM DDR3 8GB 1600MHz Kingston CL10, and I can't find another one in any major tech provider in my country. So can I combine DIMM DDR3 8GB 1600MHz Kingston CL11 or DIMM DDR3 8GB 1600MHz Kingston HyperX Savage CL9 with it?

This is my motherboard
Gigabyte Technology Co., Ltd. 970A-DS3P (CPU 1)

UPDATE: I've managed to find Kingston DIMM DDR3 8GB 1600MHz HyperX Fury Red CL10, HX316C10FR/8

Will that fit in with my original RAM? I mean the "stats" are the same.
UPDATE2:
I've also found
KHX1600C10D3B1/8G 8GB 2Rx8 1G x 64-Bit DDR3-1600 CL10 240-Pin DIMM
It seems to fit in better with my original RAM.
 
Solution


I could write a small book on DRAM timings. Most DRAM modules are marketed with three or four timings in the form of Tcl-Trcd-Trp-Tras. An effective Tras can be calculated so it's not always labelled, but some vendors like to tighten it up a bit.

Tcl = Column Latency. This is the number of DRAM bus cycles between issuing a column read operation on an open row and the strobe corresponding to the first word of the DRAM burst.

Trcd = Row to Column Delay. This is the number...


Yes you can. There's always a small risk that the modules simply won't work together, but the firmware will configure all of the memory modules to the fastest commonly supported column latency.
 

Oggi-Wan

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Jan 23, 2014
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10,530
But some memories fit better than the others, no? That's partially my question, what's the next best thing if I can't find the exact same memory?

UPDATE: I've managed to find Kingston DIMM DDR3 8GB 1600MHz HyperX Fury Red CL10, HX316C10FR/8
Will that fit in with my original RAM? I mean the "stats" are the same.
UPDATE2:
I've also found
KHX1600C10D3B1/8G 8GB 2Rx8 1G x 64-Bit DDR3-1600 CL10 240-Pin DIMM
It seems to fit in better with my original RAM.
 

Kohwali

Reputable
Jun 15, 2014
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5,660


What do latencies mean and how do they affect performance?
 


I could write a small book on DRAM timings. Most DRAM modules are marketed with three or four timings in the form of Tcl-Trcd-Trp-Tras. An effective Tras can be calculated so it's not always labelled, but some vendors like to tighten it up a bit.

Tcl = Column Latency. This is the number of DRAM bus cycles between issuing a column read operation on an open row and the strobe corresponding to the first word of the DRAM burst.

Trcd = Row to Column Delay. This is the number of DRAM bus cycles between issuing a Row Active command and the first cycle in which a column operation (read or write) may be issued.

Trp = Row Precharge. This is the number of DRAM bus cycles that it takes to close an open row. A Row Active command (opening a new row) may be issued after Trp has elapsed.

Tras = Row Active Time / Row Address Strobe. This is the minimum number of cycles between the Row Active command (opening the row) and Precharge command (closing the row).

These timings are used by the memory controller to synchronise memory operations and data on the DRAM IO bus. DDR3 has 8 independent banks per rank to work with so the memory controller can interleave memory operations. It may issue a read to one bank, then issue a read to a second bank, then read a burst from a third bank, then open a row on a fourth bank, then go back to the first bank to receive the results of the read command.

Tighter timings can sometimes result in slightly better performance but it is generally negligible. A good DDR3 controller can keep the DRAM bus busy nearly 100% of the time, which means that higher data rates almost always trump lower latency.
 
Solution