1866 CAS 8 vs. 2133 CAS 9?

SS12 · Dec 8, 2014

Here is my build:

http://pcpartpicker.com/p/HLfzWZ

So I have a common dilemma. So in my build I have G. Skill 1866Mhz CAS 8 ram for about $84, but I saw the G. Skill 2133Mhz CAS 9 ram for about $60. Links:

1866: https://pcpartpicker.com/part/gskill-memory-f314900cl8d8gbxm

2133: https://pcpartpicker.com/part/gskill-memory-f32133c9d8gxl

The answer might seem obvious, but I don't know the sweetspot for build and I've seen mixed answers as to which one to choose. Take into mind I plan to overclock. What is the sweet spot for the Asus Z97 Pro? Is the difference in latency worth the difference in price?

There also other 1866 memory sticks CAS 9 that are much cheaper than this one as well. I've considered 1600 ram as well, but I'd like to get the best bang for my buck. Thanks in advance!

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spooky2th · Dec 8, 2014

There's not gonna be a lot of difference between the two. Might get a small handful of FPS with the 2133MHz. But the CAS8 is a tighter/better speed. You'll probably have to OC your CPU to get the sticks to 2133MHz. 1866MHz, maybe not.

Dark Lord of Tech · Dec 8, 2014

You wouldn't notice a real world difference.

SS12 · Dec 8, 2014

My CPU is an i5 4690k, which accepts 1600 RAM. But an XMP profile will get around that. Is the price difference worth the difference in latency? And what do you mean when you say I would have to OC my CPU just to get to 1866Mhz?

Sorry about all the questions; I'm a bit of newby here.

Beezy · Dec 8, 2014

8/1866 = 42.87 nanoseconds
9/2133 = 42.19 nanoseconds

technically the 2133 is faster, but nothing you would notice, ever. Also more real world factors go into the speed of the RAM besides CAS and MHz. (mobo, CPU mem controller etc)

Dark Lord of Tech · Dec 8, 2014

BUY whatever is cheaper.

geofelt · Dec 8, 2014

Yes, the ram will perform within 1-2% in actual app performance or fps.
Here are some tests.
http://www.anandtech.com/show/7364/memory-scaling-on-haswell

One thing to note is that to go faster than 1866, you will need more than 1.5v to run. Probably 1.6 or 1.65v.
That has an impact on how high you can overclock.

Just an opinion, 1.5v 1866 is the sweet spot.
And... get low profile ram.

Dark Lord of Tech · Dec 8, 2014

http://www.hardwaresecrets.com/article/Understanding-RAM-Timings/26/2
Understanding RAM timings ^

Tradesman1 · Dec 9, 2014

In short the 2133/9 will be slightly better performance wise and will primarily show if you do a lot of multi-tasking and use memory intensive appsi.e. video, imaging, CAD, VMs, etc, things like that

endeavour37a · Dec 9, 2014

Beezy :

Not to nitpick but.......
A nanosecond (ns) is an SI unit of time equal to one billionth of a second (10−9 or 1/1,000,000,000 s). The answers to your divisions are 0.004287 and 0.004219 respectively, 4.287 and 4.219 milliseconds. Thought nanoseconds sounded a bit fast....

Beezy · Dec 9, 2014

endeavour37a :

Beezy :

Not to nitpick but.......
A nanosecond (ns) is an SI unit of time equal to one billionth of a second (10−9 or 1/1,000,000,000 s). The answers to your divisions are 0.004287 and 0.004219 respectively, 4.287 and 4.219 milliseconds. Thought nanoseconds sounded a bit fast....

lol thank you for clearing that up

Pinhedd · Dec 11, 2014

Beezy :

You're both wrong.

DRAM timings are measured in clock cycles, not bus transfers.

DDR3-2133 is not 2133Mhz SDRAM, it is 1066Mhz SDRAM. Both the command clock (which synchronizes the commands) and strobes (which synchronize the data transfers) are periodic and oscillate at nominally 1066Mhz. Data is transferred onto the bus with the rising and falling edge of the strobe for two transfers per cycle, or double-data-rate.

A 1066Mhz clock has a clock period of 0.9381 nanoseconds, or 938.1 picoseconds. A DDR3-2133 module with a nine cycle column latency (CAS9) will have to wait nine cycles between the issuance of a read command and the first word of the resulting burst being stable on the IO bus (accompanied by a strobe); the data on the IO bus will change ever half cycle until all eight words of the burst have been transferred.

In this case

Tcl = 9 * 0.9381 = 8.443 nanoseconds

Tburst = 4 * 0.9381 = 4.221 nanoseconds.

The first word of the burst is stable after 8.443 nano seconds, and the last word is stable after 11.72 nanoseconds. At 12.664 seconds the first word of the next read command (if one is issued) will be sent onto the IO pins.

In the grand scheme of things, CAS latency is almost completely inconsequential. A good memory controller can keep the IO bus busy nearly 100% by pipelining commands and interleaving banks.

Beezy · Dec 11, 2014

Pinhedd :

Beezy :

You're both wrong.

DRAM timings are measured in clock cycles, not bus transfers.

DDR3-2133 is not 2133Mhz SDRAM, it is 1066Mhz SDRAM. Both the command clock (which synchronizes the commands) and strobes (which synchronize the data transfers) are periodic and oscillate at nominally 1066Mhz. Data is transferred onto the bus with the rising and falling edge of the strobe for two transfers per cycle, or double-data-rate.

A 1066Mhz clock has a clock period of 0.9381 nanoseconds, or 938.1 picoseconds. A DDR3-2133 module with a nine cycle column latency (CAS9) will have to wait nine cycles between the issuance of a read command and the first word of the resulting burst being stable on the IO bus (accompanied by a strobe); the data on the IO bus will change ever half cycle until all eight words of the burst have been transferred.

In this case

Tcl = 9 * 0.9381 = 8.443 nanoseconds

Tburst = 4 * 0.9381 = 4.221 nanoseconds.

The first word of the burst is stable after 8.443 nano seconds, and the last word is stable after 11.72 nanoseconds. At 12.664 seconds the first word of the next read command (if one is issued) will be sent onto the IO pins.

In the grand scheme of things, CAS latency is almost completely inconsequential. A good memory controller can keep the IO bus busy nearly 100% by pipelining commands and interleaving banks.

Wow thanks for the super informative reply, pinhead! I'd love to look into it more do you have a good source for this info and perhaps similar info for other hardware? My degree at uni doesn't go into it so much

spooky2th · Dec 11, 2014

SS12 :

About OC'ing the CPU for higher memory speeds, your CPU is rated at 1600MHz & 1333MHz memory. Any higher memory will default to one of those speeds depending on the memory model. Maybe/Probably can OC memory to 1866MHz with no CPU overclocking. But any higher will need an OC of the CPU.

http://cpuboss.com/cpu/Intel-Core-i5-4690K

Scroll down to "memory controller."

endeavour37a · Dec 11, 2014

Thank you Penhedd for making me research this a bit deeper, must say memory is not a straight forward easy thing to understand, at least for my simple brain. But I think I understand it a bit better now thanks to you pointing out Beezy and I had it all wrong. There are many factors to consider about this when saying what is better than another thing, which is faster. And I agree 100% with you as most here do that the right answer to this question is "You won't sense any difference between 1866/8 and 2133/9 in what you use your rig for, splitting picoseconds is not relevant to gaming or much else a normal person does, perhaps bragging rights and benchmark scores are the only real value in it".

Now I know DDR3-XXXX refers to the data rate in MT/s and is NOT the memory bus clock that I assumed it was. The bus clock runs at half the transfer rate, so 1866 DDR3 runs at 933Mhz and 2133 runs at 1066Mhz. Picked up a few more things reading through all of this but the technical aspects to memory are not really easy to lay out for the types of questions we get here, but glad you did as it got me looking. I don’t fully understand this by a long shot but still reading…….

https://en.wikipedia.org/wiki/DDR2_SDRAM
https://en.wikipedia.org/wiki/DDR3_SDRAM
https://en.wikipedia.org/wiki/Transfer_%28computing%29
https://en.wikipedia.org/wiki/Memory_timings
https://en.wikipedia.org/wiki/SDRAM_latency
https://en.wikipedia.org/wiki/CAS_latency#cite_note-eighthword-6

To transfer a GB of data with either memory, the difference in time is only 9ms. Got here from using the 8th word time in a transfer burst to fill a cache line of 64 bytes on the CPU from the 64-bit bus on the DDR3. So it would take 15,625,000 transfers burst to get 1GB, given 12.33ns (1866/8) and 11.72ns (2133/9) for an 8 word burst I come up with 192ms and 183ms, 9ms difference for 1GB. Does this sound right or am I still missing something?

Pinhedd · Dec 11, 2014

endeavour37a :

A good memory controller can keep the IO bus busy nearly 100% of the time. There's always going to be a few cycles in which no useful operation can be performed (such as when selecting a new rank when the command rate is 2T or greater) and others in which the contents of the transaction queue just simply don't line up with the open pages or the timings don't permit the operation to complete within the time window.

Given the tough to analyze and non-deterministic nature of DRAM it's usually sufficient to analyze performance on the basis of theoretical peak transfer rate. 2133 megatransfers per second * 64 bits per transfer / 8 bits per byte = 17.064 gigabytes per second per memory channel. This works out to about 5.88 milliseconds per gigabyte on average at a minimum. If they were all sequential (they wouldn't be, they would span multiple rows) there would be a Tcl delay between the command to read the first address and the first word, and a Tcl + Tburst delay between the command to read the last address and the last word. There would also be a Tccd delay between read operations.
The reason for this is that it's possible to pipeline column operations. It is possible to issue a column read operation to a bank that has another column read operation in progress provided that a timing constraint is met. This timing constraint is the column command delay or Tccd. Tccd is lower bounded by Tburst, meaning that Tccd cannot be lower than 4 cycles (or 4Tck), but on certain memory architectures it may be greater than 4 cycles. This allows one burst to begin immediately after another burst finishes.

Now, 17.064 gigabytes per second for DDR3-2133 is a theoretical maximum and would be perfectly valid if DRAM/SDRAM had the same behavioural mechanics as SRAM/SSRAM. However, while SRAM has deterministic latency, SDRAM does not. The throughput of SDRAM is heavily dependant on the temporal and spatial locality of the data that's being accessed.

endeavour37a · Dec 11, 2014

Please give me a minute here....

gskill support · Dec 11, 2014

http://www.intel.com/content/www/us/en/gaming/extreme-memory-profile-xmp.html

1866 CAS 8 vs. 2133 CAS 9?

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