32 64 bits and ram perpetual doubt

ppdemo

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May 15, 2013
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i need if you can remove all doubt because I think there is much confusion over the network, this is the point:
If I have w7 64bit and programs / application that I run is 32 bits (most are installed on the x86) it can use more ram if the 32-bit program was installed on a 32-bit OS?
I ask because I am not clear about the limitation of memory, the ram memory come to be limited only by the operating system i used or also by a 32 bits applications?
because otherwise I do not understand why i would add more ram on a 64bit OS (example 8 gb) if the majority of the games are 32 bits and I have seen these are installed in x86 folder ... well I hope answers and Greetings community
 
Solution


On x86 microprocessors running in protected mode (AKA...
Hi,
It seems that the answer is that several x32 apps running simultaneously can use more than 4 GB, but one app individually is limited to 4GB, or
each 32 bit application can make use of memory more than 4 GB but each process still can not cross 4 GB barrier. Still not sure.
http://blogs.citrix.com/2011/10/13/wow64-memory-mapping-of-32bit-apps-running-on-a-64bit-windows/
 

Mackara

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Dec 20, 2014
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If you run 32bit apps in 64bit OS they can use max 4GB memory each from free memory. So if you got 16GB of memory and over 12GB is free, then 3 32bit apps can use 4GB of memory each. 64bit app (eg. that WOW64) can use as much as there is free memory.

So 32bit app can use memory above 4gb area in 64bit OS if that was your question.

32bit OS can handle only up to 4GB of memory so applications can only use what there is left.
 


On x86 microprocessors running in protected mode (AKA 32-bit mode), long mode (AKA 64-bit mode), or compatibility mode (32-bit on 64-bit mode), program code executes in what's known as a virtual address space. Virtual memory addresses are translated into physical addresses through two mechanisms, segmentation and paging. Combined, these form a process known as Virtual to Physical Address Translation.

Segmented addressing is fast but obsolete, and is completely depreciated in 64-bit mode. Paging is where the fun stuff happens. The page translation process (called a page table walk) translates a virtual address into a physical address.

In protected mode and compatibility mode, the virtual address is 32-bits in size (4 bytes); this means that any single virtual address space (each process has its own) can address at most 4GiB of memory regardless of how that memory is laid out. The size of the physical address space varies though. Starting with the first 32-bit microprocessor (30386) it was 32-bits, and this continued through the Pentium MMX. These platforms could not support more than 4GiB of memory without using complicated bank-switching hardware.
In 1995 Intel introduced the Pentium Pro which featured the Physical Address Extension (PAE) technology which, when enabled, allows the size of the physical address space to exceed 32-bits. When PAE is not enabled, the physical address space is 32 bits and is each address is represented by 4-byte values so a protected-mode/compatibility-mode address translation without PAE is 32-bits to 32-bits. With PAE the physical address space is 36-bits or greater (44 bits is the current maximum used in Intel's high end Xeon E7 microprocessors) and each address is represented by an 8-byte (64-bit value). Ergo, when PAE is enabled, a protected-mode or compatibility-mode translation is 32-bit to 64-bit (of which at most 44 are used right now).

What this means is that if an operating system gives each process its own unique virtual address space, each process can address at most 4GiB of memory, but if PAE is enabled a 32-bit operating system can manage much more than 4GiB of memory. If more than 4GiB of memory is installed, a single process can't possibly address all of it at once but two or more processes might be able to. This is very useful for servers which may have many services running at once, but less useful for consumer platforms which typically focus on one application at a time.

Microsoft has supported PAE since Windows 2000, and 32-bit versions of Windows 8 require PAE to operate. Client versions of Windows are limited to 4GiB of physical address space even when PAE is enabled; this is done primarily for marketing reasons to push users to adopt the more secure 64-bit versions of Windows. Server versions of Windows are not affected by this limitation.

In long-mode, the virtual address space is increased to 48 bits, with virtual addresses being represented by 8-bytes (some of the bits aren't used). Physical addresses remain at 36 bits or greater and are similarly represented by 8-byte values (again, some bits just aren't used). When long-mode is used, each memory translation is 64-bit to 64-bit (of which 48 and 36+ are used). Ergo, when in long mode a process can address essentially all of the memory in the machine.
 
Solution


Yes and no.

The page table walk is two levels in a non-PAE protected mode environment (10 bit level 2 + 10 bit level 1 + 12 bit offset = 32 bits), three levels in a PAE protected mode environment (2 bit level 3 + 9 bit level 2 + 9 bit level 1 + 12 bit offset = 32 bits), and four levels in a long mode environment (9 bits each for levels 4, 3, 2, and 1 as well as a 12 bit offset = 48 bits).

Without PAE enabled each page is 4KiB in size (that's where the 12 bit offset comes from), but with PAE enabled or in long mode each page can be 4KiB in size, 2MiB in size (inserted one level higher in the page table hierarchy for a 21 bit offset), or 1GiB in size (inserted two levels higher for a 30 bit offset)

When paging was introduced with the 80386 it was hardly ever used because of the amount of operational overhead involved in simply performing the translation. Segmented addressing is much, much faster but it is also far less flexible and far more problematic. A cache for the most recently used page translation entries was quickly added to the microarchitecture, this is called the TLB; it's usually implemented alongside the microprocessor's L1 and L2 I/D caches. Keep an eye out for it when reading reviews. As a result of incremental improvements to the TLB, the performance impact from going from purely segmented protected mode, to protected mode with paging, to protected mode with PAE, to long mode is negligible on current microprocessors.

User processes do not manage their own physical memory at all, they manage only their own virtual memory and must invoke the operating system to have that memory allocated to them. The existence of the virtual address space provides the process with the illusion that it owns the machine rather than that it is actually sharing it with other processes. What this means is that an application doesn't care if the operating system has enabled paging (paging is required for long mode though), or enabled PAE (PAE is also required for long mode). It's the operating system's job to ensure that the system calls from each mode are handled properly. When a 32-bit process is run in compatibility mode, it performs just like it would in long mode but at most 32 bits of the virtual address are used. Given that this would render the fourth level as always-zero it would seem to yield a possible optimization but I'm not sure if this is taken advantage of.