bgunner :
Without having to retype this all here is a link that will give you almost all the answers you seek. http://www.hardwaresecrets.com/article/Understanding-RAM-Timings/26
Ah yes, another article that manages to get a huge number of significant technical details incorrect.
@OP: CAS Latency, or Column Latency, is the number of clock cycles between the DDR SDRAM chip beginning a read command, and the first word of the DDR SDRAM burst being written to the IO bus.