Relation between tRCD and DRAM clock speed

gokussj9

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May 3, 2011
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Hi All,

I was looking to find out the relation between tRCD- row to column access delay timing parameter and the DRAM clock frequency. Is this parameter directly and proportionally dependent on the clock speed? For example, if I want to emulate a memory frequency of 800 MHz on a 1600 MHz stick with tRCD of 10, will changing tRCD to 20 do it ( I have seen it in a research paper, hence the query)?

Thanks.
 
Solution


Tcl, Trcd, Trp, and Tras are all provided in the manufacturer's datasheet on a per speed bin basis. They are usually measured in nanoseconds. For SDRAM they will be a multiple of Tck (the clock period) for that particular speed been.

For example, on one Hynix chip the minimum Tcl, Trcd, and Trp for DDR3-800 are 15ns each. This...


Tcl, Trcd, Trp, and Tras are all provided in the manufacturer's datasheet on a per speed bin basis. They are usually measured in nanoseconds. For SDRAM they will be a multiple of Tck (the clock period) for that particular speed been.

For example, on one Hynix chip the minimum Tcl, Trcd, and Trp for DDR3-800 are 15ns each. This corresponds to DDR3-800E with 6-6-6 timings. Note that Tck = 1/400E6 seconds and 6/400E6 = 15 nanoseconds.

Moving up to DDR3-1600 drops the same three timings to 13.75ns each, which is DDR3-1600K, with 11-11-11 timings. Note that Tck = 1/800E6 seconds, and 11/800E6 = 13.75 nanoseconds

It's not possible to "emulate" a slower memory frequency by changing timings, memory controllers just don't work that way. If you want to run memory at a slower data rate, just lower the data rate and set the timings accordingly. If you have a DDR3-1600 module with 10-10-10 timings, you may be able to run it at DDR3-800D (5-5-5) timings but it may not work at under DDR3-800E (6-6-6)
 
Solution