PCIe Lanes CPU vs Motherboard?

So on Intel's webpage, there is information for each CPU on how many PCIe lanes it has. But then, motherboards, particularly different chipsets, have PCIe lanes specified. Could someone explain to me the difference between the two?
 
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Besides what devices uses it, nothing. The cpu does not set max. For example, z170 would have 16 to the cpu and 20 for the mobo. That's a total of 36 not 16. Both the mobo and cpu each have a pcie controller. As far as using them for gpus, the issue is you need them for the other devices and they don't get remapped. The other pcie lanes from the mobo are used for other slots: pcie x1, m.2, usb 3.1, etc.

Well then you may ask, why don't they just not have those devices so you can use more gpus. Well intel is limiting the link between the cpu and chipset. Dmi 3.0 is only equivalent to pcie 3.0 x4. This may pose another question. How can you have x4 from chipset to cpu when the mobo has 20x, don't you need 20x to the cpu? No. While it...
the cpu sets the max.

the motherboard sets how they're used. you can tell how many pci-e lanes are used at each pci-e access point by the x16/x8/x4/x1 after it. The number tells you the max number of lanes that point will take.

So if you have a cpu with 24 pci-e lanes max and a motherboard with 3 pci-e 3.0x16 connections, you know that only 1 of those will run in full pci-e3.0x16 with that cpu.
 


Thank you for your explanation! It's still very confusing trying to piece it all together visually in my head. I may come back with questions soon.
 
Hello... It seems to be the "Popular - New" prefer'd' Device maker/Consumer level Communication protocol, gearing their NEW products there too... There will be New types of access to PCIe 3 , you will start to notice... and a application to a certain Consumer... So you will start to right now see Confusing "Consumer" options and chipset versions... Untill the products find their "niche" and uses to this fast Data bus... OR Untill they invent something faster...
 


...What?
 
Hello... LOL!!! sorry if a few cells got jingled there in that response...

In the electrical industry they create a Standard for how a electrical device so Works/Communicates... for Industry Device Makers and use - design... in simple terms a (Standard - ISO) is created by experts/scientists... So... here it is...

https://en.wikipedia.org/wiki/PCI_Express

It's large... Wanna cover a chapter of it? B )

Watch out for the future (2017?)... Brave Posters... For Terms now for PCIe 4.0 standard HAVE already been created and defined for the Industry B O
 
Besides what devices uses it, nothing. The cpu does not set max. For example, z170 would have 16 to the cpu and 20 for the mobo. That's a total of 36 not 16. Both the mobo and cpu each have a pcie controller. As far as using them for gpus, the issue is you need them for the other devices and they don't get remapped. The other pcie lanes from the mobo are used for other slots: pcie x1, m.2, usb 3.1, etc.

Well then you may ask, why don't they just not have those devices so you can use more gpus. Well intel is limiting the link between the cpu and chipset. Dmi 3.0 is only equivalent to pcie 3.0 x4. This may pose another question. How can you have x4 from chipset to cpu when the mobo has 20x, don't you need 20x to the cpu? No. While it may need to communicate to the cpu, it won't be using that much dmi bandwidth and just uses its own to its devices. Gpus are really the only thing that will be using a high bandwidth to the cpu so get the full bandwidth. You maybe thinking of other scenarios of high end computing maybe with a pcie ssd but then you look at the speed and you aren't getting 4GB/s and if you are, you are on a x16 slot so aren't having a bottleneck issue. You just don't see how much thought really goes into things and why they are how they are.

When the mobo manufactuer gives a block diagram for the mobo, it maybe easier for you to piece it all together visually in your head. http://www.legitreviews.com/wp-content/uploads/2015/08/z170-deluxe-block-diagram.jpg
 
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