To answer your first question, I have no idea. I'd need a bit more context, as I am not an expert by any means. I think I may be out of my league answering this. That said, I did find something useful for your second question, regarding DQS.
https://www.micron.com/~/media/documents/products/technical-note/dram/tn4605.pdf
Special thanks to Micro for keeping that PDF online for no apparent reason. Also, to Google, for helping me to find it.
Now, if you refer to page 4, it reads (I am copying this in the event you, or someone else, cannot access the PDF in the future):
Strobe-Based Data Bus
In a purely synchronous system, data output and
capture are referenced to a common, free-running sys-
tem clock. However, the maximum data rate for such a
system is reached when the sum of output access time
and flight time approaches the bit time (the reciprocal
of the data rate). Although generating delayed clocks
for early data launch and/or late data capture will allow
for increased data rate, these techniques do not ac-
count for the fact that
the data valid window (or data
eye) moves relative to any fixed clock signal, due to
changes in temperature, voltage, or loading. So, to al-
low for even higher data rates, data strobe signals were
added to DDR devices. The data strobes are nonfree-
running signals driven by the device, which is driving
the data signals (the controller for WRITEs, the DRAMs
for READs). At the DRAM device level, for READs, the
data strobe (DQS) signals are effectively additional
data outputs (DQ) with a predetermined pattern; for
WRITEs, the strobe signals are used as clocks to cap-
ture the corresponding input data. At the board level,
the strobe signals have identical loading to data sig-
nals and should be routed similarly.
If I find anything else, I can let you know.
P.S. Additional stuff that I thought you may be interested in, but I didn't think warranted inclusion in the main response.
http://www.transcend-info.com/Support/FAQ-296
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