Something like a HUB or adapter for RAM?

Hi,

Only Intel's Xeon-E7 series microprocessors can handle absurd amounts of memory. This is accomplished by employing a memory architecture that is dissimlar to (but not necessarily incompatible with) that found in consumer desktops.

In practice, commercial CPUs are limited to 4 unbuffered ranks of memory per DRAM channel, or 8 registered (partially buffered) ranks of memory per DRAM channel when registered memory is supported. Fully-Buffered/Load-Reduced ranks raises this to in the neighbourhood of 12-16 ranks per channel, which is simply obscene.

For unstacked DDR3, the highest density available is 4 gigabits per chip. 4 gigabits per chip, 8 chips per rank yields 4 gigabytes per rank, or a maximum of 16 gigabytes per channel. This is why most LGA-11xx motherboards advertise support for 32GiB of memory, two channels at 16GiB each is the maximum that is natively supported. Some advertise support for 64GiB in anticipation of 8 gigabit native DDR3 (none exist) or include custom support for 8-gigabit stacked DDR3. By comparison, the LGA-2011 series CPUs have 4 memory channels, supporting up to 64GiB natively or 128GiB with non-standard configurations. The use of registered memory in servers extends this by several factors.

A fully loaded Xeon E-7 server will still have 4 memory channels per LGA-2011-1 CPU that is installed, but the external interface is different. Rather than communicate with the DRAM chips directly using the DDR3/DDR4 command protocols, Xeon-E7 CPUs communicate with the external memory buffer, called Jordan Creek, via the Scalable Memory Interface (SMI) protocol.

Each Jordan Creek buffer provides two external DDR3/DDR4 channels for a total of 8 effective channels per socket. The memory buffer can operate the channels independently for incredible capacity and performance, or in lockstep (essentially applying RAID-1 logic to system memory) for enterprise level reliability. Each Jordan Creek channel can support up to 3 DIMMs, for a total of 6 DIMMs per JC buffer. A single DIMM can have capacities up to 64GiB, for an incredible total of 1.5TiB of memory per socket, or up to 12 TiB of memory in an 8 socket system.

This kind of capacity from a single CPU is simply impossible using current fabrication methods. Each external buffer supplies the power for all of the ranks connected to it as well as the internal state logic for the DRAM ranks that are connected to it. Integrating all of this onto one chip would result in a very large and very power hungry chip with an impossibly complex IO interface.