ECC RAM Parity

firefoxx04

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Jan 23, 2009
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Quick question about ECC ram.

I know ECC ram can be configured in some sort of fail over or redundant setup as long as the motherboard supports it.

I am running a basic AMD board that supports ECC. I have 8GB of RAM and it shows up as 8GB of RAM. My question is, does the ECC require some sort of parity overhead in order to work?

Like RAID5 requires one drives capacity to be sacrificed for parity. Is ECC the same way?

Seems like a silly question at first but now I am thrown for a loop on how ECC works when you are not losing any capacity.
 
Solution


Parity and ECC are two separate mechanisms.

Parity provides a single additional bit per n bits of data, with n commonly being 8. The sole purpose of parity is to determine if an error...
Parity and ECC are different. Parity is that every 8 bits has one extra bit. So 8 bits becomes 9, 32 becomes 36, 64 becomes 72 and so on and so forth. ECC has these extra bits and a chip that helps to correct errors it finds, only use is in servers. Parity memory, however, does the same thing but each extra bit is individually accessible so it is a bit more powerful.

As far as I know memory has never had a redundancy feature like RAID just the ability to correct errors.
 

Saberus

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Older high-end servers like the HP DL740 had memory RAID, ran just like RAID5. It wasn't around for very long, though, I think it just wasn't worth the overhead in cost and complexity. But memory RAID has never been in consumer gear that I know of. (Unless you count mirroring, which is like RAID1) Memory RAID is an interesting experiment that arrived perhaps a bit too late to gain a foothold, as the memory instabilities it addressed were becoming rarer, easier to detect, and correctable with simpler means.

As my two cents to the OP, the extra bits needed for ECC to work are already there, and just aren't counted towards the end value the system reports. Count the packages, it will be a multiple of nine, plus one or two that are a different size and shape. 8GB of ECC is really 9GB, but that extra 1GB is used only to make sure the 8 you see are correct.
 

TJ Hooker

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Parity is one form of error detection. It can tell you if an error has occurred (only in case of single bit errors), but cannot correct the error. It is arguably the simplest and weakest form of bit error detection. I don't know what method ECC RAM uses, but it would have to be something that can detect and correct errors, e.g. Hamming code.
 


Parity and ECC are two separate mechanisms.

Parity provides a single additional bit per n bits of data, with n commonly being 8. The sole purpose of parity is to determine if an error occured somewhere in those n bits. Parity is extremely simple. The parity bit is 1 if the number of 1s in the original n-bit word is odd, and the parity bit is 0 if the number of 1s in the original n-bit word is even.

Parity allows for the detection but not correction of single bit errors within the word to which they relate.

ECC uses a SECDED (Single Error Correction, Double Error Detection) Hamming code configuration. In most cases, either 32 bits of data are encoded to 38 bits (5 bit code + 1 bit global parity) or 64 bits of data are encoded to 72 bits (7 bit code + 1 bit global parity).

Of particular interest is that providing parity for 64 bits is commonly performed by an additional 8-bit DRAM chip for a total of 9 chips per rank (or two 4-bit DRAM chips for 18). This extends the total bus to 72 bits, 64 data and 8 parity. ECC is similarly implemented by adding a 9th or 17th+18th chip to extend the total bus to 72 bits. Therefore, ECC has the exact same spatial overhead on the DIMM as parity. In other words, a parity DIMM and an ECC DIMM are usually identical.

The DRAM buses fanned out from Intel's and AMD's memory controllers have these extra data lines pulled high whenever the ECC/Parity DRAM chip is missing.
 
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