Question about RAM latency !!!

While I appreciate that you are both trying to be helpful, you're both completely wrong.

Synchronous DRAM (SDRAM) timings are measured in clock cycles. DDR SDRAM transfers data twice per clock cycle, once on the rising edge of the clock, and once on the falling edge of the clock.

DDR3 and DDR4 both use burst lengths of eight, which means that every read command results in eight words being transferred from the selected SDRAM rank to the memory controller, and that every write command results in eight words being transferred from the memory controller to the selected SDRAM rank.

CAS latency, or Column Address Strobe latency, is more appropriately described as read-to-data-ready delay. It's the amount of time, measured in clock cycles, between a read command being latched on the Command Bus, and the first word of the ensuing burst being strobed onto the IO bus. Subsequent words are strobed every half cycle with the eighth word being strobed 3.5 cycles after the first word has been strobed; it follows logically that the first word of the next read command will be strobed 4 cycles after the first word of the referenced read command. This important timing, called Tburst, is a constant of 4 cycles for DDR3 and DDR4, and a constant of 2 cycles for DDR2.

DDR4-2400 has a reference clock of 1,200Mhz and DDR4-3000 has a reference clock of 1,500Mhz.

The clock period for DDR4-2400 is 1/(1.2E9) = 833 picoseconds

The clock period for DDR4-3000 is 1(1.5E9) = 666 picoseconds.

Time to first word for DDR4-2400 CAS 15
15 * 833 ps = 12.5 ns

Time to first word for DDR4-3000 CAS 18
18 * 666 ps = 12 ns

Time to eighth word for DDR4-2400 CAS 15
(15 * 833 ps) + (3.5 * 833 ps) = 15.41 ns

Time to eighth word for DDR4-3000 CAS 18
(18 * 666 ps) + (3.5 * 666 ps) = 14.3 ns

Time to sixteenth word for DDR4-2400 CAS 15
(15 * 833 ps) + (7.5 * 833 ps) = 18.75 ns

Time to sixteenth word for DDR4-3000 CAS 18
(18 * 666 ps) + (7.5 * 666 ps) = 17 ns

DDR4-3000 CAS 18 not only has 25% more bus bandwidth, but it gets data to and from the ranks noticeably quicker, moreso when the data is pipelined.

At the end of the day, memory controllers are tasked with keeping the SDRAM IO busses busy. As long as they're kept busy, CAS is of very little importance.