CPU Lanes vs MOBO Lanes

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BLACKBERREST3

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I have done research on both and I know this may seem overdone, but every other answer I have come across has gone over my head. This is for all chipsets and CPUs and not a specific one. If a CPU has a certain amount of lanes and a MOBO has a certain amount of lanes, how much bandwidth do you actually get? DMI 3.0 has a max transfer of 4x pcie 3.0 lanes or 32gt/s, so how can a MOBO have more than 4 lanes? Does it reassign those extra lanes in the MOBO to add up to 4x pcie lanes?
 
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The mobo has a PCIe switch that splits the lanes between the CPU and PCH (i.e. DMI 3.0) into however many lanes the mobo has. However, the bandwidth to the CPU (e.g. PCIe 3.0 x4) is shared between all mobo PCIe lanes, so PCIe devices connected to mobo lanes will be throttled if multiple devices try to communicate with the CPU at once such that the total bandwidth would be greater than 4 PCIe lanes could provide.

Imagine a gigabit ethernet switch with 4 ports, and Devices A, B, C, and D plugged in. B, C, and D can all communicate with A at 1 Gb/s, but only one at a time. If B and C try to talk to A simultaneously, both B and C will only get 500 Mb/s to A. If B, C, and D all try to talk to A at the same time, they'll all only get 333 Mb/s
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kanewolf

kanewolf

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It can have more because a USB 2.0 port doesn't use an entire lane (for example). Just like a gigabit network switch might have 48 gigabit bandwidth, it only has that if all ports are active. Each endpoint (port in my example) has a limited bandwidth that is less than the total available. Those 4x PCIe lanes between the motherboard and CPU are multiplexed in time and oversubscribed because the assumption is that EVERY USB port and SATA port and network port won't be 100% busy all the time.
 
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TJ Hooker

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The mobo has a PCIe switch that splits the lanes between the CPU and PCH (i.e. DMI 3.0) into however many lanes the mobo has. However, the bandwidth to the CPU (e.g. PCIe 3.0 x4) is shared between all mobo PCIe lanes, so PCIe devices connected to mobo lanes will be throttled if multiple devices try to communicate with the CPU at once such that the total bandwidth would be greater than 4 PCIe lanes could provide.

Imagine a gigabit ethernet switch with 4 ports, and Devices A, B, C, and D plugged in. B, C, and D can all communicate with A at 1 Gb/s, but only one at a time. If B and C try to talk to A simultaneously, both B and C will only get 500 Mb/s to A. If B, C, and D all try to talk to A at the same time, they'll all only get 333 Mb/s
 
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Solution
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junkeymonkey

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PCI Express link performance

https://en.wikipedia.org/wiki/PCI_Express

then

http://ark.intel.com/products/82012/Intel-Z97-Chipset

so like z97 you see 16 lanes from the cpu and 8 from the chipset - how there shared / configured or not is up to the boards manufacture

so single card is full x16 dual card is 8x8
if a 3ed slot is shared it can be 16/8x4x4 and so on

then from the chipset 8 lanes at any configuration of x1, x2, x4

then use a chart like from winki to see the bandwidth corresponding

 
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BLACKBERREST3

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That makes sense, so it is shared between lanes. Now I just have to explain what I have learned in another topic regarding a diy das/nas/san. How do I pick 2 answers as the solution?
 
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kanewolf

kanewolf

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You can only pick one. You can "vote up" for multiple but only one best answer ...
 
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