- Dec 26, 2017
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Guys/Gals -studying for my certs and getting kind of confused when it comes to double date rate such as DDR3-1066 and how that number (for example 1066 MHz) relates or is limited by the speed of the overall frontside bus. 
Perhaps I'm not reading this correctly, but as I understand it, for DDR3-1066 you'd be pulling off an I/O of 533 MHz and a clock speed of 266 MHz (DDR2, DDR3 throughput is measured off double and quadrupled I/O circuitry respectively). 1066 MHz from what I've read refers to the speed at which data can be pulled off memory and put onto the external data bus for processing.
My question is where does frontside bus speed come into play? If frontside bus speed for example is only 100 MHz it seems like all that extra speed in memory (in this example 1066 MHz) cannot be utilized because you are limited by the frontside bus speed (100 MHz).
Am I reading this correctly? Can someone please help explain?
Thanks.
Perhaps I'm not reading this correctly, but as I understand it, for DDR3-1066 you'd be pulling off an I/O of 533 MHz and a clock speed of 266 MHz (DDR2, DDR3 throughput is measured off double and quadrupled I/O circuitry respectively). 1066 MHz from what I've read refers to the speed at which data can be pulled off memory and put onto the external data bus for processing.
My question is where does frontside bus speed come into play? If frontside bus speed for example is only 100 MHz it seems like all that extra speed in memory (in this example 1066 MHz) cannot be utilized because you are limited by the frontside bus speed (100 MHz).
Am I reading this correctly? Can someone please help explain?
Thanks.
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