how does and how many does DDR4 work faster than DDR3?

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arash.12372

Mar 2, 2018
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hi guys. i am researching about different operation strategy of ddr3 and ddr4 memories. i know that the tccd is the delay between successive column commands in ddr3. also, ddr4 has two type of tccd: one for successive column commands to banks of same bank group named tccd-L and second is the delay between successive column commands to banks of different bank groups, named tccd-S.
as i know, ddr4 does not doubled the width and frequency of memory chip internal data bus. what i can understand with these knowledges is that, the tccd of ddr3 must be equal to to tccd-S of ddr4 if the memory array frequency be equal in both type of ram. so how ddr4 can operate faster than ddr3?
i will be helpful using an example in explanations.
 
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Pinhedd

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Aug 7, 2007
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You've pretty much answered your own question.

Doubling the prefetch depth or doubling the number of banks would have resulted in unacceptable complexity and power consumption while still maintaining a constant 4 cycle Tccd regardless of which bank is the subject of the column command. The solution to this problem, bank groups, were first used in GDDR5.

If you take a look at DDR4 data sheets, Tccd_S and Tccd_L don't diverge right away. The first few DDR4 speed bins still have Tccd_S = Tccd_L = 4; it's only when the IO bus speed increases that Tccd_L begins to increase while Tccd_S remains at 4.

Allowing unlocked behaviour between bank groups while maintaining locked behaviour within bank groups permitted the number of banks on the chip to be doubled both without causing the power consumption of the front end to explode and without causing the front-end logic to slow down unacceptably.
 
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arash.12372

Mar 2, 2018
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thank for your consideration. but what i can not understand is that, how ddr4 operates to double the IO Data Rate than DDR3? something must be doubled in chip side or memory controller to achieving this improvement. if it is the number of memory addresses (requests) sent from DDR4 Memory Controller, the speed of something must be doubled also in chip. if not, so what is the change?
 
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