ahh where did you get the idea that the P4 does NOT beat everything the P3 does.
as I have mentioned before, the P4 requires P4 code as it is a ground up new CPU totally different than the P3.
the P3's compiled software and SSE 1 instructions do not work effiencely for the P4 as it does not understand many or executes the p3 code more slowly
when you compare a p4 with P4 optimized code it does everything better than the P3..
the P4 has many new features, including 144 SSE 2 inst.
dual 3 ghz FP units, totally different 20 stage pipeline,
it can issue more instructions per clock, has 8 way new Die cache, etc et c
if you look at the engineering books for the 2 as I have
it states they are very different...
again as for RAMBUS it is not useless to increase bandwidth,
as bandwidth has been saturated with P3 and AMD above 900 mhz.. with SDRAM
that is why you get the law of dimishing returns as you go faster CPU's
RAMBUS and DDR big contribution is bandwidth,
becasue SDRAM could only do around 700 MPS, and that is not fast enough, therefore the memory is the bottleneck
whereas rambus allows 3.2 GPS plenty of hearroom till
2.5 ghz P4
P4 requires bandwidth and throughput, as it is much faster almost double that of P3 in many areas,
so using the example of P3 with DDR and RAMBUS is bad as the CPU was not fast enough to make a difference...
the P4 is and you have to hammer it with huge loads to even start to show its throughput and ability..
latency is an overused word that has little meaning
these days with very fast CPU's and chipsets.
if you have a latency of 5 for example but when executing you can deliver 5 Gigs of data
you are still better off than a latency of 2.5
delivering only 2 gigs of data
the are degrees and applications of latency..
anyway.. back to my email
have a good weekend
Cameron
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