Archived from groups: comp.sys.ibm.pc.hardware.chips (
More info?)
On Tue, 06 Apr 2004 18:03:19 -0400, George Macdonald
<fammacd=!SPAM^nothanks@tellurian.com> wrote:
>On Tue, 06 Apr 2004 07:14:55 -0400, Tony Hill <hilla_nospam_20@yahoo.ca>
>wrote:
>>Well, as we've mentioned a few times before, Intel's P4 and AMD's
>>AthlonXP are NOT 100% compatible as it is. Same goes for Intel's P4
>>vs. Intel's PIII.
>
>You mean wrt to SSE, SSE2, SSE3, 3DNOW etc.? I don't really think of those
>as "compatibility" issues.
No, I'm mostly referring to the fact that some of the odd-ball and
seldom used instructions in the x86 ISA will return slightly different
values when executed on different chips. Often it's something so
small as what flags are set after the instruction is executed and you
almost never run into any problems from these.
Most of these differences are just documented as "Errata" or
"Specification Updates", and while occasionally a new stepping will be
released to fix them, as often as not they are simply left as is.
Some of the differences aren't even documented as errata as they
simply depend on what chip you're comparing against. If AMD is
comparing their chips to the Pentium and Intel compares their chips to
the PII, they will come up with slight differences
>> However the same code generally works on both
>>unless you really go out of your way to use the incompatible code.
>>There are certainly going to be a few rather minor differences between
>>AMD64 and Intel's EMT64/IA-32e/name-of-day, but compilers should be
>>able to take care of them with no trouble at all.
>
>It would still be interesting to know what they came up with but I don't
>have the spare $$ for the report. The thought of paying for it, just to
>find out it was something already fairly well known would be a umm
>disappointment.
The suggestion of "probing" for the CPU type could
>just mean SSE3 or it could be something more subtle.
Well, they could be talking about things like the CMPXCHG8
instructions, used to compare and exchange 8 byte value. This
instruction is supported on some chips but not on others (I know VIA
chips do not support it, I'm not sure about AMD's line-up though). Or
there are things like the No-Execute bit for pages, enabled on AMD's
Opteron and Athlon64 in 64-bit Long mode but not on Intel's current
chips.
When you've got as much baggage as x86 has, there are lots of little
things that you need to check for.
>>The only problem Intel might have is running code that has already
>>been compiled for AMD's chips before any differences between them
>>became known. However, this is simply the price that Intel has to pay
>>for arriving WAY late to the game (IMO AMD was late to the game and
>>they've still got a year and a half's head start).
>
>I'm sure Intel will (try to) find a way to not "pay" here.
I have the
>feeling that game market is where they could get hurt most here, for one
>reason or another.
Could be, though fortunately most games come with the ability to be
patched, so it would be a simple matter of downloading a new patch to
fix any problems.
Tony
-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca