Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

http://www.theregister.co.uk/2004/ [...] _strained/

Though this story is about the new 90nm process using strained-silicon
techniques, it's also known that the older 130nm process also uses it. This
is kind of interesting because both IBM and Intel were competing against
each other to introduce this stuff, and you didn't hear whether AMD would
introduce it too, but it looks like they did, and very quietly.

Yousuf Khan

--
Humans: contact me at ykhan at rogers dot com
Spambots: just reply to this email address ;-)

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan wrote:
>
> http://www.theregister.co.uk/2004/ [...] _strained/
>
> Though this story is about the new 90nm process using strained-silicon
> techniques, it's also known that the older 130nm process also uses it. This
> is kind of interesting because both IBM and Intel were competing against
> each other to introduce this stuff, and you didn't hear whether AMD would
> introduce it too, but it looks like they did, and very quietly.
>
> Yousuf Khan

But Pentium M also uses 90nm process. They don't seem to have the same
problems as the Prescotts? Something don't add up.

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Johannes H Andersen wrote:
> Yousuf Khan wrote:
>>
>> http://www.theregister.co.uk/2004/ [...] _strained/
>>
>> Though this story is about the new 90nm process using
>> strained-silicon techniques, it's also known that the older 130nm
>> process also uses it. This is kind of interesting because both IBM
>> and Intel were competing against each other to introduce this stuff,
>> and you didn't hear whether AMD would introduce it too, but it looks
>> like they did, and very quietly.
>>
>> Yousuf Khan
>
> But Pentium M also uses 90nm process. They don't seem to have the same
> problems as the Prescotts? Something don't add up.

Don't they? I seem to recall that the Dothans were delayed early on too.
It's obvious that Intel is fixing them one product at a time as they go on.

Yousuf Khan

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Johannes H Andersen wrote:
>
> Yousuf Khan wrote:
>
>>http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
>>
>>Though this story is about the new 90nm process using strained-silicon
>>techniques, it's also known that the older 130nm process also uses it. This
>>is kind of interesting because both IBM and Intel were competing against
>>each other to introduce this stuff, and you didn't hear whether AMD would
>>introduce it too, but it looks like they did, and very quietly.
>>
>> Yousuf Khan
>
>
> But Pentium M also uses 90nm process. They don't seem to have the same
> problems as the Prescotts? Something don't add up.

http://zdnet.com.com/2100-1103-5317169.html

<quote>

Although AMD is not divulging many details about its strained silicon,
the company's technology differs from the way IBM and Intel incorporate
it, the AMD representative said.

<snip>

AMD is more localized, Thomas Sonderman, the company's director of
automated precision manufacturing technology, told The Semiconductor
Reporter. The AMD representative would not comment on Sonderman's
remark, but other AMD executives and researchers have described
localized straining as a process in which only certain parts of a chip
are affected. It is unclear whether AMD's technology will provide the
same level of performance improvement.

</quote>

Guess we'll find out in time what that really means.

RM

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Robert Myers wrote:
> AMD is more localized, Thomas Sonderman, the company's director of
> automated precision manufacturing technology, told The Semiconductor
> Reporter. The AMD representative would not comment on Sonderman's
> remark, but other AMD executives and researchers have described
> localized straining as a process in which only certain parts of a chip
> are affected. It is unclear whether AMD's technology will provide the
> same level of performance improvement.
>
> </quote>
>
> Guess we'll find out in time what that really means.

There were some previous stories about where AMD said that almost all
silicon is "strained" to a certain extent anyways. I think the distinction
between what is highly strained and what is just normally strained is
subjective.

Yousuf Khan

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
<johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:
>Yousuf Khan wrote:
>>
>> http://www.theregister.co.uk/2004/ [...] _strained/
>>
>> Though this story is about the new 90nm process using strained-silicon
>> techniques, it's also known that the older 130nm process also uses it. This
>> is kind of interesting because both IBM and Intel were competing against
>> each other to introduce this stuff, and you didn't hear whether AMD would
>> introduce it too, but it looks like they did, and very quietly.
>
>But Pentium M also uses 90nm process. They don't seem to have the same
>problems as the Prescotts? Something don't add up.

Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
were 6 months late to ship, I would say that it had a few problems of
it's own.

If your referring more to the power consumption side of things, then
no the Dothan didn't have big issues, but it also has FAR fewer logic
transistors than Prescott. In fact, for a chip with 60M+ logic
transistors, the Prescott's power consumption really isn't
unexpectedly high. The real question that no one at Intel seems to be
able to answer is how they managed to more than double the number of
transistors (vs. Northwood) and not have anything to show for it.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

"Tony Hill" <hilla_nospam_20@yahoo.ca> wrote in message news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
> On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
> <johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:

> The real question that no one at Intel seems to be
> able to answer is how they managed to more than double the number of
> transistors (vs. Northwood) and not have anything to show for it.

Whaddaya mean?! Greater heat output, which gives justification for BTX.
(hehe, will they ever be able to live this down?)

AJ

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

"Yousuf Khan" <bbbl67@ezrs.com> writes:

> Robert Myers wrote:
>> AMD is more localized, Thomas Sonderman, the company's director of
>> automated precision manufacturing technology, told The Semiconductor
>> Reporter. The AMD representative would not comment on Sonderman's
>> remark, but other AMD executives and researchers have described
>> localized straining as a process in which only certain parts of a chip
>> are affected. It is unclear whether AMD's technology will provide the
>> same level of performance improvement.
>>
>> </quote>
>>
>> Guess we'll find out in time what that really means.
>
> There were some previous stories about where AMD said that almost all
> silicon is "strained" to a certain extent anyways. I think the distinction
> between what is highly strained and what is just normally strained is
> subjective.

[Caveat: it's been more than 10 years since I worked with
semiconductor physics during my thesis work. Time flies]

Just adding the dopants (phosporous, boron, etc) will create a minute
strain in the silicon due to the difference in lattice constant.
IIRC, it is only noticable in the most heavily doped N-regions and
then as a small reduction of mobility. And MOS tranistors usually
deploy lower dopant levels than the emitter regions of bipolar
transistors.

Also, the areas near other materials (oxide, nitride) are normally
strained (compressed, I believe). SiGe is well-known for being
strained because Germanium has a lattice constant approx 4,2% bigger
than Silicon. Too much heat or a too thick SiGe layer will cause the
strained layer to relax, ie develop cracks.

I guess that what AMD is trying to say, without actually saying it, is
that it is only the region right under the gate is strained. Which
points either to some kind of selective deposition technique related
to the gate oxide, or a masking step resulting in leaving the strained
in only the areas directly below the gate oxide.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
> On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
> <johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:
> >Yousuf Khan wrote:
> >>
> >> http://www.theregister.co.uk/2004/ [...] _strained/
> >>
> >> Though this story is about the new 90nm process using strained-silicon
> >> techniques, it's also known that the older 130nm process also uses it.
This
> >> is kind of interesting because both IBM and Intel were competing
against
> >> each other to introduce this stuff, and you didn't hear whether AMD
would
> >> introduce it too, but it looks like they did, and very quietly.
> >
> >But Pentium M also uses 90nm process. They don't seem to have the same
> >problems as the Prescotts? Something don't add up.
>
> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
> were 6 months late to ship, I would say that it had a few problems of
> it's own.

The problems were supposedly due to circuit design issues.

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

In article <41271bfb$0$274$edfadb0f@dread14.news.tele.dk>,
Sirannon <rune_no***spamaagaard@hotmail.com> wrote:
>
>"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
>news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
>>
>> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
>> were 6 months late to ship, I would say that it had a few problems of
>> it's own.
>
>The problems were supposedly due to circuit design issues.

Moving to new processes has been getting gradually harder, but many
people were taken aback just HOW much harder it was to produce viable
CPUs on the 90 nm process than on the 130 nm one. I should be very
surprised if we see the 65 nm process on what is currently stated to
be its schedule.

This is almost certainly a major part of the cause that Intel has
been juggling its roadmap (e.g. cancelling Tejas), and is definitely
the reason that AMD have got into bed with IBM.


Regards,
Nick Maclaren.

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Kai Harrekilde-Petersen wrote:
> I guess that what AMD is trying to say, without actually saying it, is
> that it is only the region right under the gate is strained. Which
> points either to some kind of selective deposition technique related
> to the gate oxide, or a masking step resulting in leaving the strained
> in only the areas directly below the gate oxide.

That makes some sense about how AMD might be putting the strain in. Does it
make any difference how much strain there is in the lattice?

Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
metal cools down, it cools down in several points at once and therefore the
crystals start forming is several locations at once. As the crystals run
into each other, you end up with a material with differently oriented
crystals at the microscopic level. My impression is that in semiconductor
wafers this is not the case, that they have found a way to make a single
wafer with a single crystal structure throughout. Is this impression wrong?
If not, and the wafer is a single crystal, if you put strain only in some
parts of the crystal and not others, wouldn't you have a warpy wafer after
that?

Yousuf Khan

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

"Yousuf Khan" <bbbl67@ezrs.com> writes:

> Kai Harrekilde-Petersen wrote:
>> I guess that what AMD is trying to say, without actually saying it, is
>> that it is only the region right under the gate is strained. Which
>> points either to some kind of selective deposition technique related
>> to the gate oxide, or a masking step resulting in leaving the strained
>> in only the areas directly below the gate oxide.
>
> That makes some sense about how AMD might be putting the strain in. Does it
> make any difference how much strain there is in the lattice?

Indeed yes. The strain changes the lattice constant, and hence a
number of fundamental parameters of the Silicon. One of the
parameters that is affected is the effective mobility of the carriers
and thereby the speed of the transistors.

> Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
> metal cools down, it cools down in several points at once and therefore the
> crystals start forming is several locations at once.

Chip production techniques are very very very far away from heat-cast
techniques. Chip production use sputtering, variations of chemical
vapor deposition (CVD, LPCVD, UHV-CVD) and molecular beam epitaxy
(MBE) techniques, depending on how much material you want to grow: MBE
can acchieve fractional atom layer control while sputtering is used
for metalization depostion, where up to micron-thick layers are
needed.

> As the crystals run
> into each other, you end up with a material with differently oriented
> crystals at the microscopic level. My impression is that in semiconductor
> wafers this is not the case, that they have found a way to make a single
> wafer with a single crystal structure throughout. Is this impression wrong?

You are correct. Quite a lot of effort is put into making ingots of
single crystal Silicon. There are two methods of producing silicon
ingots that I am aware of: the Czochralski technique and the
float-zone process. The Czochralski method is to take a small seed
ingot (~1" diameter) of known quality and lattice orientation and dip
it into a melt of silicon. By slowly pulling the seed up from the
melt and using rotation to obtain a reasonably round ingot, the melten
silicon will attach to the seed crystal forming a lattice and
orientation matched ingot. These ingots can be as long as up to 2
meters (~6'7" ), and with 8" or 12" diameter (depending on what wafer
size you want). The ingot is then polished, marked with flats (to
indicate n/p type material and lattice orientation), and sawn into
wafers. Each wafer is then polished to a mirror level finish (the side
that will be used for processing). The lattice orientation is mostly
important for GaAs due to orientation dependant mobility and for
micromechanics, where orientation dependant etches (KOH) is used.

These ingots have lattice fault densities as the parts-per-billion
level. For even higher quality, and more uniform distribution of
dopants, the ingot can be taken through the float-zone process where
an RF field is used to melt the ingot in a thin belt. Above and below
the floating zone, the ingot is rotated in reverse direction to each
other. Since impurities (and dopants) tend to have either a higher or
lower solubility in molten silicon than in solid silicon, the
impurities can be cleaned out of the main ingot by performing multiple
float-zone passes. Super-high voltage devices require as low impurity
and lattice fault densities as you can get, since local concentrations
of impurities or lattice faults function as seeds for voltage
breakdown. For perfectly uniform lightly n-doped ingots, undoped
ingots are taken to a neutron-irradiation chamber where some of the
neutrons combine with the silicon atoms to become phosporous atoms
(and some excess energy emitted as gamma and beta rays). Since the
penetration depth of neutrons in silicon is about 100cm, a very high
uniformity can be acchieved.

> If not, and the wafer is a single crystal, if you put strain only in some
> parts of the crystal and not others, wouldn't you have a warpy wafer after
> that?

Well, considering that the wafer 500um thick (mostly for mechanical
strength during production), and the stressed layer is at mode a few
nanometers, the wafer doesn't warp. Also, remember that the strain is
usually quite minute, mechanically seen. But electrically, the strain
is measurable.

Regards,


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

Kai Harrekilde-Petersen wrote:
>
> "Yousuf Khan" <bbbl67@ezrs.com> writes:
>
> > Kai Harrekilde-Petersen wrote:
> >> I guess that what AMD is trying to say, without actually saying it, is
> >> that it is only the region right under the gate is strained. Which
> >> points either to some kind of selective deposition technique related
> >> to the gate oxide, or a masking step resulting in leaving the strained
> >> in only the areas directly below the gate oxide.
> >
> > That makes some sense about how AMD might be putting the strain in. Does it
> > make any difference how much strain there is in the lattice?
>
> Indeed yes. The strain changes the lattice constant, and hence a
> number of fundamental parameters of the Silicon. One of the
> parameters that is affected is the effective mobility of the carriers
> and thereby the speed of the transistors.
>
> > Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
> > metal cools down, it cools down in several points at once and therefore the
> > crystals start forming is several locations at once.
>
> Chip production techniques are very very very far away from heat-cast
> techniques. Chip production use sputtering, variations of chemical
> vapor deposition (CVD, LPCVD, UHV-CVD) and molecular beam epitaxy
> (MBE) techniques, depending on how much material you want to grow: MBE
> can acchieve fractional atom layer control while sputtering is used
> for metalization depostion, where up to micron-thick layers are
> needed.
>
> > As the crystals run
> > into each other, you end up with a material with differently oriented
> > crystals at the microscopic level. My impression is that in semiconductor
> > wafers this is not the case, that they have found a way to make a single
> > wafer with a single crystal structure throughout. Is this impression wrong?
>
> You are correct. Quite a lot of effort is put into making ingots of
> single crystal Silicon. There are two methods of producing silicon
> ingots that I am aware of: the Czochralski technique and the
> float-zone process. The Czochralski method is to take a small seed
> ingot (~1" diameter) of known quality and lattice orientation and dip
> it into a melt of silicon. By slowly pulling the seed up from the
> melt and using rotation to obtain a reasonably round ingot, the melten
> silicon will attach to the seed crystal forming a lattice and
> orientation matched ingot. These ingots can be as long as up to 2
> meters (~6'7" ), and with 8" or 12" diameter (depending on what wafer
> size you want). The ingot is then polished, marked with flats (to
> indicate n/p type material and lattice orientation), and sawn into
> wafers. Each wafer is then polished to a mirror level finish (the side
> that will be used for processing). The lattice orientation is mostly
> important for GaAs due to orientation dependant mobility and for
> micromechanics, where orientation dependant etches (KOH) is used.
>
> These ingots have lattice fault densities as the parts-per-billion
> level. For even higher quality, and more uniform distribution of
> dopants, the ingot can be taken through the float-zone process where
> an RF field is used to melt the ingot in a thin belt. Above and below
> the floating zone, the ingot is rotated in reverse direction to each
> other. Since impurities (and dopants) tend to have either a higher or
> lower solubility in molten silicon than in solid silicon, the
> impurities can be cleaned out of the main ingot by performing multiple
> float-zone passes. Super-high voltage devices require as low impurity
> and lattice fault densities as you can get, since local concentrations
> of impurities or lattice faults function as seeds for voltage
> breakdown. For perfectly uniform lightly n-doped ingots, undoped
> ingots are taken to a neutron-irradiation chamber where some of the
> neutrons combine with the silicon atoms to become phosporous atoms
> (and some excess energy emitted as gamma and beta rays). Since the
> penetration depth of neutrons in silicon is about 100cm, a very high
> uniformity can be acchieved.
>
> > If not, and the wafer is a single crystal, if you put strain only in some
> > parts of the crystal and not others, wouldn't you have a warpy wafer after
> > that?
>
> Well, considering that the wafer 500um thick (mostly for mechanical
> strength during production), and the stressed layer is at mode a few
> nanometers, the wafer doesn't warp. Also, remember that the strain is
> usually quite minute, mechanically seen. But electrically, the strain
> is measurable.
>
> Regards,
>
> Kai
> --
> Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

Thanks for that Kai, the best explanation I've seen for a long time.

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cg76u5$cbs$1@pegasus.csx.cam.ac.uk...
> In article <41271bfb$0$274$edfadb0f@dread14.news.tele.dk>,
> Sirannon <rune_no***spamaagaard@hotmail.com> wrote:
> >
> >"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
> >news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
> >>
> >> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
> >> were 6 months late to ship, I would say that it had a few problems of
> >> it's own.
> >
> >The problems were supposedly due to circuit design issues.
>
> Moving to new processes has been getting gradually harder, but many
> people were taken aback just HOW much harder it was to produce viable
> CPUs on the 90 nm process than on the 130 nm one. I should be very
> surprised if we see the 65 nm process on what is currently stated to
> be its schedule.
>
> This is almost certainly a major part of the cause that Intel has
> been juggling its roadmap (e.g. cancelling Tejas), and is definitely
> the reason that AMD have got into bed with IBM.

The main process challenges at 65nm are more or less solved.
using a combination of SOI, lowk interconnects,
and strain. The issue remaining is how Intel is going to
make use of it, and whether they're going to mess up as
they did with the Prescott's design.

Longer term, lowk apparently has limited usefulness. So
completely new interconnects are going to be need
probably by 45nm, and certainly at anything lower.