Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (
More info?)
Kai Harrekilde-Petersen wrote:
>
> "Yousuf Khan" <bbbl67@ezrs.com> writes:
>
> > Kai Harrekilde-Petersen wrote:
> >> I guess that what AMD is trying to say, without actually saying it, is
> >> that it is only the region right under the gate is strained. Which
> >> points either to some kind of selective deposition technique related
> >> to the gate oxide, or a masking step resulting in leaving the strained
> >> in only the areas directly below the gate oxide.
> >
> > That makes some sense about how AMD might be putting the strain in. Does it
> > make any difference how much strain there is in the lattice?
>
> Indeed yes. The strain changes the lattice constant, and hence a
> number of fundamental parameters of the Silicon. One of the
> parameters that is affected is the effective mobility of the carriers
> and thereby the speed of the transistors.
>
> > Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
> > metal cools down, it cools down in several points at once and therefore the
> > crystals start forming is several locations at once.
>
> Chip production techniques are very very very far away from heat-cast
> techniques. Chip production use sputtering, variations of chemical
> vapor deposition (CVD, LPCVD, UHV-CVD) and molecular beam epitaxy
> (MBE) techniques, depending on how much material you want to grow: MBE
> can acchieve fractional atom layer control while sputtering is used
> for metalization depostion, where up to micron-thick layers are
> needed.
>
> > As the crystals run
> > into each other, you end up with a material with differently oriented
> > crystals at the microscopic level. My impression is that in semiconductor
> > wafers this is not the case, that they have found a way to make a single
> > wafer with a single crystal structure throughout. Is this impression wrong?
>
> You are correct. Quite a lot of effort is put into making ingots of
> single crystal Silicon. There are two methods of producing silicon
> ingots that I am aware of: the Czochralski technique and the
> float-zone process. The Czochralski method is to take a small seed
> ingot (~1" diameter) of known quality and lattice orientation and dip
> it into a melt of silicon. By slowly pulling the seed up from the
> melt and using rotation to obtain a reasonably round ingot, the melten
> silicon will attach to the seed crystal forming a lattice and
> orientation matched ingot. These ingots can be as long as up to 2
> meters (~6'7"), and with 8" or 12" diameter (depending on what wafer
> size you want). The ingot is then polished, marked with flats (to
> indicate n/p type material and lattice orientation), and sawn into
> wafers. Each wafer is then polished to a mirror level finish (the side
> that will be used for processing). The lattice orientation is mostly
> important for GaAs due to orientation dependant mobility and for
> micromechanics, where orientation dependant etches (KOH) is used.
>
> These ingots have lattice fault densities as the parts-per-billion
> level. For even higher quality, and more uniform distribution of
> dopants, the ingot can be taken through the float-zone process where
> an RF field is used to melt the ingot in a thin belt. Above and below
> the floating zone, the ingot is rotated in reverse direction to each
> other. Since impurities (and dopants) tend to have either a higher or
> lower solubility in molten silicon than in solid silicon, the
> impurities can be cleaned out of the main ingot by performing multiple
> float-zone passes. Super-high voltage devices require as low impurity
> and lattice fault densities as you can get, since local concentrations
> of impurities or lattice faults function as seeds for voltage
> breakdown. For perfectly uniform lightly n-doped ingots, undoped
> ingots are taken to a neutron-irradiation chamber where some of the
> neutrons combine with the silicon atoms to become phosporous atoms
> (and some excess energy emitted as gamma and beta rays). Since the
> penetration depth of neutrons in silicon is about 100cm, a very high
> uniformity can be acchieved.
>
> > If not, and the wafer is a single crystal, if you put strain only in some
> > parts of the crystal and not others, wouldn't you have a warpy wafer after
> > that?
>
> Well, considering that the wafer 500um thick (mostly for mechanical
> strength during production), and the stressed layer is at mode a few
> nanometers, the wafer doesn't warp. Also, remember that the strain is
> usually quite minute, mechanically seen. But electrically, the strain
> is measurable.
>
> Regards,
>
> Kai
> --
> Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
Thanks for that Kai, the best explanation I've seen for a long time.
Speaking as a customer, we are already VERY
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