AMD quietly introduces locally-strained silicon process

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/

Though this story is about the new 90nm process using strained-silicon
techniques, it's also known that the older 130nm process also uses it. This
is kind of interesting because both IBM and Intel were competing against
each other to introduce this stuff, and you didn't hear whether AMD would
introduce it too, but it looks like they did, and very quietly.

Yousuf Khan

--
Humans: contact me at ykhan at rogers dot com
Spambots: just reply to this email address ;-)
26 answers Last reply
More about quietly introduces locally strained silicon process
  1. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Yousuf Khan wrote:
    >
    > http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
    >
    > Though this story is about the new 90nm process using strained-silicon
    > techniques, it's also known that the older 130nm process also uses it. This
    > is kind of interesting because both IBM and Intel were competing against
    > each other to introduce this stuff, and you didn't hear whether AMD would
    > introduce it too, but it looks like they did, and very quietly.
    >
    > Yousuf Khan

    But Pentium M also uses 90nm process. They don't seem to have the same
    problems as the Prescotts? Something don't add up.
  2. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Johannes H Andersen wrote:
    > Yousuf Khan wrote:
    >>
    >> http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
    >>
    >> Though this story is about the new 90nm process using
    >> strained-silicon techniques, it's also known that the older 130nm
    >> process also uses it. This is kind of interesting because both IBM
    >> and Intel were competing against each other to introduce this stuff,
    >> and you didn't hear whether AMD would introduce it too, but it looks
    >> like they did, and very quietly.
    >>
    >> Yousuf Khan
    >
    > But Pentium M also uses 90nm process. They don't seem to have the same
    > problems as the Prescotts? Something don't add up.

    Don't they? I seem to recall that the Dothans were delayed early on too.
    It's obvious that Intel is fixing them one product at a time as they go on.

    Yousuf Khan
  3. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Johannes H Andersen wrote:
    >
    > Yousuf Khan wrote:
    >
    >>http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
    >>
    >>Though this story is about the new 90nm process using strained-silicon
    >>techniques, it's also known that the older 130nm process also uses it. This
    >>is kind of interesting because both IBM and Intel were competing against
    >>each other to introduce this stuff, and you didn't hear whether AMD would
    >>introduce it too, but it looks like they did, and very quietly.
    >>
    >> Yousuf Khan
    >
    >
    > But Pentium M also uses 90nm process. They don't seem to have the same
    > problems as the Prescotts? Something don't add up.

    http://zdnet.com.com/2100-1103-5317169.html

    <quote>

    Although AMD is not divulging many details about its strained silicon,
    the company's technology differs from the way IBM and Intel incorporate
    it, the AMD representative said.

    <snip>

    AMD is more localized, Thomas Sonderman, the company's director of
    automated precision manufacturing technology, told The Semiconductor
    Reporter. The AMD representative would not comment on Sonderman's
    remark, but other AMD executives and researchers have described
    localized straining as a process in which only certain parts of a chip
    are affected. It is unclear whether AMD's technology will provide the
    same level of performance improvement.

    </quote>

    Guess we'll find out in time what that really means.

    RM
  4. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
    <johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:
    >Yousuf Khan wrote:
    >>
    >> http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
    >>
    >> Though this story is about the new 90nm process using strained-silicon
    >> techniques, it's also known that the older 130nm process also uses it. This
    >> is kind of interesting because both IBM and Intel were competing against
    >> each other to introduce this stuff, and you didn't hear whether AMD would
    >> introduce it too, but it looks like they did, and very quietly.
    >
    >But Pentium M also uses 90nm process. They don't seem to have the same
    >problems as the Prescotts? Something don't add up.

    Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
    were 6 months late to ship, I would say that it had a few problems of
    it's own.

    If your referring more to the power consumption side of things, then
    no the Dothan didn't have big issues, but it also has FAR fewer logic
    transistors than Prescott. In fact, for a chip with 60M+ logic
    transistors, the Prescott's power consumption really isn't
    unexpectedly high. The real question that no one at Intel seems to be
    able to answer is how they managed to more than double the number of
    transistors (vs. Northwood) and not have anything to show for it.

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
  5. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Robert Myers wrote:
    > AMD is more localized, Thomas Sonderman, the company's director of
    > automated precision manufacturing technology, told The Semiconductor
    > Reporter. The AMD representative would not comment on Sonderman's
    > remark, but other AMD executives and researchers have described
    > localized straining as a process in which only certain parts of a chip
    > are affected. It is unclear whether AMD's technology will provide the
    > same level of performance improvement.
    >
    > </quote>
    >
    > Guess we'll find out in time what that really means.

    There were some previous stories about where AMD said that almost all
    silicon is "strained" to a certain extent anyways. I think the distinction
    between what is highly strained and what is just normally strained is
    subjective.

    Yousuf Khan
  6. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    "Tony Hill" <hilla_nospam_20@yahoo.ca> wrote in message news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
    > On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
    > <johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:

    > The real question that no one at Intel seems to be
    > able to answer is how they managed to more than double the number of
    > transistors (vs. Northwood) and not have anything to show for it.

    Whaddaya mean?! Greater heat output, which gives justification for BTX.
    (hehe, will they ever be able to live this down?)

    AJ
  7. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    "Yousuf Khan" <bbbl67@ezrs.com> writes:

    > Robert Myers wrote:
    >> AMD is more localized, Thomas Sonderman, the company's director of
    >> automated precision manufacturing technology, told The Semiconductor
    >> Reporter. The AMD representative would not comment on Sonderman's
    >> remark, but other AMD executives and researchers have described
    >> localized straining as a process in which only certain parts of a chip
    >> are affected. It is unclear whether AMD's technology will provide the
    >> same level of performance improvement.
    >>
    >> </quote>
    >>
    >> Guess we'll find out in time what that really means.
    >
    > There were some previous stories about where AMD said that almost all
    > silicon is "strained" to a certain extent anyways. I think the distinction
    > between what is highly strained and what is just normally strained is
    > subjective.

    [Caveat: it's been more than 10 years since I worked with
    semiconductor physics during my thesis work. Time flies]

    Just adding the dopants (phosporous, boron, etc) will create a minute
    strain in the silicon due to the difference in lattice constant.
    IIRC, it is only noticable in the most heavily doped N-regions and
    then as a small reduction of mobility. And MOS tranistors usually
    deploy lower dopant levels than the emitter regions of bipolar
    transistors.

    Also, the areas near other materials (oxide, nitride) are normally
    strained (compressed, I believe). SiGe is well-known for being
    strained because Germanium has a lattice constant approx 4,2% bigger
    than Silicon. Too much heat or a too thick SiGe layer will cause the
    strained layer to relax, ie develop cracks.

    I guess that what AMD is trying to say, without actually saying it, is
    that it is only the region right under the gate is strained. Which
    points either to some kind of selective deposition technique related
    to the gate oxide, or a masking step resulting in leaving the strained
    in only the areas directly below the gate oxide.


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
  8. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Kai Harrekilde-Petersen wrote:
    > I guess that what AMD is trying to say, without actually saying it, is
    > that it is only the region right under the gate is strained. Which
    > points either to some kind of selective deposition technique related
    > to the gate oxide, or a masking step resulting in leaving the strained
    > in only the areas directly below the gate oxide.

    That makes some sense about how AMD might be putting the strain in. Does it
    make any difference how much strain there is in the lattice?

    Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
    metal cools down, it cools down in several points at once and therefore the
    crystals start forming is several locations at once. As the crystals run
    into each other, you end up with a material with differently oriented
    crystals at the microscopic level. My impression is that in semiconductor
    wafers this is not the case, that they have found a way to make a single
    wafer with a single crystal structure throughout. Is this impression wrong?
    If not, and the wafer is a single crystal, if you put strain only in some
    parts of the crystal and not others, wouldn't you have a warpy wafer after
    that?

    Yousuf Khan
  9. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    "Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
    news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
    > On Fri, 20 Aug 2004 20:34:23 GMT, Johannes H Andersen
    > <johs@wsrexaoxazxsizefitterwozeoarrxzx.com> wrote:
    > >Yousuf Khan wrote:
    > >>
    > >> http://www.theregister.co.uk/2004/08/20/amd_90nm_strained/
    > >>
    > >> Though this story is about the new 90nm process using strained-silicon
    > >> techniques, it's also known that the older 130nm process also uses it.
    This
    > >> is kind of interesting because both IBM and Intel were competing
    against
    > >> each other to introduce this stuff, and you didn't hear whether AMD
    would
    > >> introduce it too, but it looks like they did, and very quietly.
    > >
    > >But Pentium M also uses 90nm process. They don't seem to have the same
    > >problems as the Prescotts? Something don't add up.
    >
    > Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
    > were 6 months late to ship, I would say that it had a few problems of
    > it's own.

    The problems were supposedly due to circuit design issues.
  10. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    In article <41271bfb$0$274$edfadb0f@dread14.news.tele.dk>,
    Sirannon <rune_no***spamaagaard@hotmail.com> wrote:
    >
    >"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
    >news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
    >>
    >> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
    >> were 6 months late to ship, I would say that it had a few problems of
    >> it's own.
    >
    >The problems were supposedly due to circuit design issues.

    Moving to new processes has been getting gradually harder, but many
    people were taken aback just HOW much harder it was to produce viable
    CPUs on the 90 nm process than on the 130 nm one. I should be very
    surprised if we see the 65 nm process on what is currently stated to
    be its schedule.

    This is almost certainly a major part of the cause that Intel has
    been juggling its roadmap (e.g. cancelling Tejas), and is definitely
    the reason that AMD have got into bed with IBM.


    Regards,
    Nick Maclaren.
  11. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    "Yousuf Khan" <bbbl67@ezrs.com> writes:

    > Kai Harrekilde-Petersen wrote:
    >> I guess that what AMD is trying to say, without actually saying it, is
    >> that it is only the region right under the gate is strained. Which
    >> points either to some kind of selective deposition technique related
    >> to the gate oxide, or a masking step resulting in leaving the strained
    >> in only the areas directly below the gate oxide.
    >
    > That makes some sense about how AMD might be putting the strain in. Does it
    > make any difference how much strain there is in the lattice?

    Indeed yes. The strain changes the lattice constant, and hence a
    number of fundamental parameters of the Silicon. One of the
    parameters that is affected is the effective mobility of the carriers
    and thereby the speed of the transistors.

    > Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
    > metal cools down, it cools down in several points at once and therefore the
    > crystals start forming is several locations at once.

    Chip production techniques are very very very far away from heat-cast
    techniques. Chip production use sputtering, variations of chemical
    vapor deposition (CVD, LPCVD, UHV-CVD) and molecular beam epitaxy
    (MBE) techniques, depending on how much material you want to grow: MBE
    can acchieve fractional atom layer control while sputtering is used
    for metalization depostion, where up to micron-thick layers are
    needed.

    > As the crystals run
    > into each other, you end up with a material with differently oriented
    > crystals at the microscopic level. My impression is that in semiconductor
    > wafers this is not the case, that they have found a way to make a single
    > wafer with a single crystal structure throughout. Is this impression wrong?

    You are correct. Quite a lot of effort is put into making ingots of
    single crystal Silicon. There are two methods of producing silicon
    ingots that I am aware of: the Czochralski technique and the
    float-zone process. The Czochralski method is to take a small seed
    ingot (~1" diameter) of known quality and lattice orientation and dip
    it into a melt of silicon. By slowly pulling the seed up from the
    melt and using rotation to obtain a reasonably round ingot, the melten
    silicon will attach to the seed crystal forming a lattice and
    orientation matched ingot. These ingots can be as long as up to 2
    meters (~6'7"), and with 8" or 12" diameter (depending on what wafer
    size you want). The ingot is then polished, marked with flats (to
    indicate n/p type material and lattice orientation), and sawn into
    wafers. Each wafer is then polished to a mirror level finish (the side
    that will be used for processing). The lattice orientation is mostly
    important for GaAs due to orientation dependant mobility and for
    micromechanics, where orientation dependant etches (KOH) is used.

    These ingots have lattice fault densities as the parts-per-billion
    level. For even higher quality, and more uniform distribution of
    dopants, the ingot can be taken through the float-zone process where
    an RF field is used to melt the ingot in a thin belt. Above and below
    the floating zone, the ingot is rotated in reverse direction to each
    other. Since impurities (and dopants) tend to have either a higher or
    lower solubility in molten silicon than in solid silicon, the
    impurities can be cleaned out of the main ingot by performing multiple
    float-zone passes. Super-high voltage devices require as low impurity
    and lattice fault densities as you can get, since local concentrations
    of impurities or lattice faults function as seeds for voltage
    breakdown. For perfectly uniform lightly n-doped ingots, undoped
    ingots are taken to a neutron-irradiation chamber where some of the
    neutrons combine with the silicon atoms to become phosporous atoms
    (and some excess energy emitted as gamma and beta rays). Since the
    penetration depth of neutrons in silicon is about 100cm, a very high
    uniformity can be acchieved.

    > If not, and the wafer is a single crystal, if you put strain only in some
    > parts of the crystal and not others, wouldn't you have a warpy wafer after
    > that?

    Well, considering that the wafer 500um thick (mostly for mechanical
    strength during production), and the stressed layer is at mode a few
    nanometers, the wafer doesn't warp. Also, remember that the strain is
    usually quite minute, mechanically seen. But electrically, the strain
    is measurable.

    Regards,


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
  12. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    "Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
    news:cg76u5$cbs$1@pegasus.csx.cam.ac.uk...
    > In article <41271bfb$0$274$edfadb0f@dread14.news.tele.dk>,
    > Sirannon <rune_no***spamaagaard@hotmail.com> wrote:
    > >
    > >"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
    > >news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
    > >>
    > >> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
    > >> were 6 months late to ship, I would say that it had a few problems of
    > >> it's own.
    > >
    > >The problems were supposedly due to circuit design issues.
    >
    > Moving to new processes has been getting gradually harder, but many
    > people were taken aback just HOW much harder it was to produce viable
    > CPUs on the 90 nm process than on the 130 nm one. I should be very
    > surprised if we see the 65 nm process on what is currently stated to
    > be its schedule.
    >
    > This is almost certainly a major part of the cause that Intel has
    > been juggling its roadmap (e.g. cancelling Tejas), and is definitely
    > the reason that AMD have got into bed with IBM.

    The main process challenges at 65nm are more or less solved.
    using a combination of SOI, lowk interconnects,
    and strain. The issue remaining is how Intel is going to
    make use of it, and whether they're going to mess up as
    they did with the Prescott's design.

    Longer term, lowk apparently has limited usefulness. So
    completely new interconnects are going to be need
    probably by 45nm, and certainly at anything lower.
  13. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    FYI, the roadmap:

    http://public.itrs.net/Files/2003ITRS/Home2003.htm


    "Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
    news:cg76u5$cbs$1@pegasus.csx.cam.ac.uk...
    > In article <41271bfb$0$274$edfadb0f@dread14.news.tele.dk>,
    > Sirannon <rune_no***spamaagaard@hotmail.com> wrote:
    > >
    > >"Tony Hill" <hilla_nospam_20@yahoo.ca> skrev i en meddelelse
    > >news:bsrdi010mvka8rn90rnk434u1508pb7p0a@4ax.com...
    > >>
    > >> Err, the Pentium-M chips produced on a 90nm process (aka 'Dothan')
    > >> were 6 months late to ship, I would say that it had a few problems of
    > >> it's own.
    > >
    > >The problems were supposedly due to circuit design issues.
    >
    > Moving to new processes has been getting gradually harder, but many
    > people were taken aback just HOW much harder it was to produce viable
    > CPUs on the 90 nm process than on the 130 nm one. I should be very
    > surprised if we see the 65 nm process on what is currently stated to
    > be its schedule.
    >
    > This is almost certainly a major part of the cause that Intel has
    > been juggling its roadmap (e.g. cancelling Tejas), and is definitely
    > the reason that AMD have got into bed with IBM.
    >
    >
    > Regards,
    > Nick Maclaren.
  14. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Kai Harrekilde-Petersen wrote:
    >
    > "Yousuf Khan" <bbbl67@ezrs.com> writes:
    >
    > > Kai Harrekilde-Petersen wrote:
    > >> I guess that what AMD is trying to say, without actually saying it, is
    > >> that it is only the region right under the gate is strained. Which
    > >> points either to some kind of selective deposition technique related
    > >> to the gate oxide, or a masking step resulting in leaving the strained
    > >> in only the areas directly below the gate oxide.
    > >
    > > That makes some sense about how AMD might be putting the strain in. Does it
    > > make any difference how much strain there is in the lattice?
    >
    > Indeed yes. The strain changes the lattice constant, and hence a
    > number of fundamental parameters of the Silicon. One of the
    > parameters that is affected is the effective mobility of the carriers
    > and thereby the speed of the transistors.
    >
    > > Also in most heat-cast mettalic materials (steel, aluminium, etc.) as the
    > > metal cools down, it cools down in several points at once and therefore the
    > > crystals start forming is several locations at once.
    >
    > Chip production techniques are very very very far away from heat-cast
    > techniques. Chip production use sputtering, variations of chemical
    > vapor deposition (CVD, LPCVD, UHV-CVD) and molecular beam epitaxy
    > (MBE) techniques, depending on how much material you want to grow: MBE
    > can acchieve fractional atom layer control while sputtering is used
    > for metalization depostion, where up to micron-thick layers are
    > needed.
    >
    > > As the crystals run
    > > into each other, you end up with a material with differently oriented
    > > crystals at the microscopic level. My impression is that in semiconductor
    > > wafers this is not the case, that they have found a way to make a single
    > > wafer with a single crystal structure throughout. Is this impression wrong?
    >
    > You are correct. Quite a lot of effort is put into making ingots of
    > single crystal Silicon. There are two methods of producing silicon
    > ingots that I am aware of: the Czochralski technique and the
    > float-zone process. The Czochralski method is to take a small seed
    > ingot (~1" diameter) of known quality and lattice orientation and dip
    > it into a melt of silicon. By slowly pulling the seed up from the
    > melt and using rotation to obtain a reasonably round ingot, the melten
    > silicon will attach to the seed crystal forming a lattice and
    > orientation matched ingot. These ingots can be as long as up to 2
    > meters (~6'7"), and with 8" or 12" diameter (depending on what wafer
    > size you want). The ingot is then polished, marked with flats (to
    > indicate n/p type material and lattice orientation), and sawn into
    > wafers. Each wafer is then polished to a mirror level finish (the side
    > that will be used for processing). The lattice orientation is mostly
    > important for GaAs due to orientation dependant mobility and for
    > micromechanics, where orientation dependant etches (KOH) is used.
    >
    > These ingots have lattice fault densities as the parts-per-billion
    > level. For even higher quality, and more uniform distribution of
    > dopants, the ingot can be taken through the float-zone process where
    > an RF field is used to melt the ingot in a thin belt. Above and below
    > the floating zone, the ingot is rotated in reverse direction to each
    > other. Since impurities (and dopants) tend to have either a higher or
    > lower solubility in molten silicon than in solid silicon, the
    > impurities can be cleaned out of the main ingot by performing multiple
    > float-zone passes. Super-high voltage devices require as low impurity
    > and lattice fault densities as you can get, since local concentrations
    > of impurities or lattice faults function as seeds for voltage
    > breakdown. For perfectly uniform lightly n-doped ingots, undoped
    > ingots are taken to a neutron-irradiation chamber where some of the
    > neutrons combine with the silicon atoms to become phosporous atoms
    > (and some excess energy emitted as gamma and beta rays). Since the
    > penetration depth of neutrons in silicon is about 100cm, a very high
    > uniformity can be acchieved.
    >
    > > If not, and the wafer is a single crystal, if you put strain only in some
    > > parts of the crystal and not others, wouldn't you have a warpy wafer after
    > > that?
    >
    > Well, considering that the wafer 500um thick (mostly for mechanical
    > strength during production), and the stressed layer is at mode a few
    > nanometers, the wafer doesn't warp. Also, remember that the strain is
    > usually quite minute, mechanically seen. But electrically, the strain
    > is measurable.
    >
    > Regards,
    >
    > Kai
    > --
    > Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

    Thanks for that Kai, the best explanation I've seen for a long time.
  15. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    In article <dULVc.7128$LV1.3360@nwrddc02.gnilink.net>,
    Raymond <nospam@aly.net> wrote:
    >
    >The main process challenges at 65nm are more or less solved.
    >using a combination of SOI, lowk interconnects,
    >and strain. The issue remaining is how Intel is going to
    >make use of it, and whether they're going to mess up as
    >they did with the Prescott's design.

    Well, maybe, but I am not so green as I am cabbage-looking. I have
    heard that before, most recently about the 90 nm process - and that
    was BEFORE the schedules started slipping. I have heard from one
    of the best sources in the industry that the leakage issues aren't
    going to be easy to resolve, and are going to bite harder at 65 nm
    than 90, even with all such technologies in operation.

    Yes, I believe that the challenges have been resolved as far as is
    needed to build CPUs, but the need is to produce marketable ones
    at an economic rate. As my source said about a 200 watt CPU, that
    is not a laptop chip :-) Speaking as a customer, we are already VERY
    concerned about the power requirements and short lifetimes of some
    high-performance CPUs. If you are trying to pack thousands into a
    small space, both are very serious issues.

    Thanks for the roadmap pointer - I will look at it when I am not on
    a 38K dialup line.

    >Longer term, lowk apparently has limited usefulness. So
    >completely new interconnects are going to be need
    >probably by 45nm, and certainly at anything lower.

    Hence the IBM-AMD linkup. I am prepared to bet that instructions
    have come down from On High: Think. With the qualification that
    that means think radically and laterally. Watch that space.


    Regards,
    Nick Maclaren.
  16. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Kai Harrekilde-Petersen wrote:
    > Indeed yes. The strain changes the lattice constant, and hence a
    > number of fundamental parameters of the Silicon. One of the
    > parameters that is affected is the effective mobility of the carriers
    > and thereby the speed of the transistors.

    Another technique that AMD was experimenting with (and has now apparently
    abandonned) was isotopically pure silicon-28 wafers, where all non-Si-28
    atoms are removed. Apparently Si-28 atoms alone make for a more regular
    lattice pattern than natural silicon. I assume this was for the same
    purposes as strained silicon since it's all got to do with keeping the
    lattice patterns as open as possible. Of course, separating out the one
    isotope of silicon from another must have been more expensive than this
    straining process.

    >> If not, and the wafer is a single crystal, if you put strain only in
    >> some parts of the crystal and not others, wouldn't you have a warpy
    >> wafer after that?
    >
    > Well, considering that the wafer 500um thick (mostly for mechanical
    > strength during production), and the stressed layer is at mode a few
    > nanometers, the wafer doesn't warp. Also, remember that the strain is
    > usually quite minute, mechanically seen. But electrically, the strain
    > is measurable.

    Okay, I see what you mean, even though the wafer is pretty thin, it's like
    miles thick compared to the etching that will eventually go on it.

    Yousuf Khan
  17. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Tony Hill wrote:

    > The real question that no one at Intel seems to be
    > able to answer is how they managed to more than double the number of
    > transistors (vs. Northwood) and not have anything to show for it.
    >

    Nothing to show for it is perhaps an overstatement, unless I am
    misreading SpecFP results:

    Intel D875PBZ motherboard (3.4 GHz, Pentium 4 processor with HT
    Technology) 1308 1300 1 Mar-2004 Config

    Intel D875PBZ motherboard (AA-301) (3.4E GHz, Pentium 4 Processor with
    HT Technology) 1485 1481 1 core, 1 chip, 1 core/chip (HT
    [enabled)] Apr-2004

    That's a bigger bump than you get from going to the extreme edition at
    the same frequency.

    The 3.4E result is with HT on and the 3.4 result is with HT off. No
    published way, so far as I can tell to sort out the effects of HT on vs.
    HT off as compared to 3.4 vs. 3.4E.

    RM
  18. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    This one should be more palatable on dialup:
    http://www.intel.com/research/silicon/micron.htm

    Basically, the outlook looks quite good for the next 5+ years.


    "Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
    news:cg86kb$5mi$1@pegasus.csx.cam.ac.uk...
    > In article <dULVc.7128$LV1.3360@nwrddc02.gnilink.net>,
    > Raymond <nospam@aly.net> wrote:
    > >
    > >The main process challenges at 65nm are more or less solved.
    > >using a combination of SOI, lowk interconnects,
    > >and strain. The issue remaining is how Intel is going to
    > >make use of it, and whether they're going to mess up as
    > >they did with the Prescott's design.
    >
    > Well, maybe, but I am not so green as I am cabbage-looking. I have
    > heard that before, most recently about the 90 nm process - and that
    > was BEFORE the schedules started slipping. I have heard from one
    > of the best sources in the industry that the leakage issues aren't
    > going to be easy to resolve, and are going to bite harder at 65 nm
    > than 90, even with all such technologies in operation.
    >
    > Yes, I believe that the challenges have been resolved as far as is
    > needed to build CPUs, but the need is to produce marketable ones
    > at an economic rate. As my source said about a 200 watt CPU, that
    > is not a laptop chip :-) Speaking as a customer, we are already VERY
    > concerned about the power requirements and short lifetimes of some
    > high-performance CPUs. If you are trying to pack thousands into a
    > small space, both are very serious issues.
    >
    > Thanks for the roadmap pointer - I will look at it when I am not on
    > a 38K dialup line.
    >
    > >Longer term, lowk apparently has limited usefulness. So
    > >completely new interconnects are going to be need
    > >probably by 45nm, and certainly at anything lower.
    >
    > Hence the IBM-AMD linkup. I am prepared to bet that instructions
    > have come down from On High: Think. With the qualification that
    > that means think radically and laterally. Watch that space.
    >
    >
    > Regards,
    > Nick Maclaren.
  19. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    nmm1@cus.cam.ac.uk (Nick Maclaren) writes:

    > Hence the IBM-AMD linkup. I am prepared to bet that instructions
    > have come down from On High: Think. With the qualification that
    > that means think radically and laterally. Watch that space.

    A coworker of mine, who is an ex-IBM employee, told of a famous IBM
    (at least internally in IBM) memo from one top executive to another
    top executive. It ran:

    Subject: Year 2000.
    Please handle.

    Given that story, a memo of just "Think" seems plausible :-)


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
  20. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    Kai Harrekilde-Petersen wrote:

    > Also, remember that the strain is
    > usually quite minute, mechanically seen. But electrically, the strain
    > is measurable.

    I'd think the strain must be huge, though over very short distances only.

    If transistors would work better when the chip is mounted under slight
    stress that would have been done long ago. Also an Si transistor would
    make a handy strain gauge which they seem not to be.

    I guess that the strain can be a few percent (see the SiGe lattice) -
    which is a lot for a brittle material. But as it is in a very thin layer
    and over short distances (areas of stretch and areas of compression
    mixed) the overall mechanical effect is negligible.

    Also, a thin layer will not store much mechanical energy which means
    that cracks will not propagate. Right? Try to stretch something as
    brottle as silicon my a few percent and you'll likely have a break
    otherwise,


    Thomas
  21. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    In article <sYYVc.6293$vH5.80@amstwist00>, Zak <jute@zak.invalid> wrote:
    >Kai Harrekilde-Petersen wrote:
    >
    >> Also, remember that the strain is
    >> usually quite minute, mechanically seen. But electrically, the strain
    >> is measurable.
    >
    >I'd think the strain must be huge, though over very short distances only.

    No, because that would lead to too much dislocation.

    >If transistors would work better when the chip is mounted under slight
    >stress that would have been done long ago. Also an Si transistor would
    >make a handy strain gauge which they seem not to be.

    I believe that some of the early laboratory experiments did precisely
    the former, but it wasn't controllable enough for production. And
    the latter has certainly been done - I don't know whether modern
    strain gauges work that way, but some did at one stage.


    Regards,
    Nick Maclaren.
  22. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    nmm1@cus.cam.ac.uk (Nick Maclaren) writes:

    > In article <sYYVc.6293$vH5.80@amstwist00>, Zak <jute@zak.invalid> wrote:
    >>Kai Harrekilde-Petersen wrote:
    >>
    >>> Also, remember that the strain is
    >>> usually quite minute, mechanically seen. But electrically, the strain
    >>> is measurable.
    >>
    >>I'd think the strain must be huge, though over very short distances only.
    >
    > No, because that would lead to too much dislocation.

    Dislocation, and lattice faults during the growth.

    >>If transistors would work better when the chip is mounted under slight
    >>stress that would have been done long ago. Also an Si transistor would
    >>make a handy strain gauge which they seem not to be.
    >
    > I believe that some of the early laboratory experiments did precisely
    > the former, but it wasn't controllable enough for production. And
    > the latter has certainly been done - I don't know whether modern
    > strain gauges work that way, but some did at one stage.

    Silicon works very nicely as a strain gauge by way of piezo-electric
    effect. Most accelerometers in cars (airbags) use a micro mechanical
    bridge with a weight at the end approach, where a diffusion resistor
    is placed on the bridge. By measuring the change in resistivity, the
    bending (and hence, the acceleration) can be determined.


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
  23. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    On Sat, 21 Aug 2004 20:39:10 GMT, Robert Myers
    <rmyers1400@comcast.net> wrote:
    >Tony Hill wrote:
    >
    >> The real question that no one at Intel seems to be
    >> able to answer is how they managed to more than double the number of
    >> transistors (vs. Northwood) and not have anything to show for it.
    >>
    >
    >Nothing to show for it is perhaps an overstatement, unless I am
    >misreading SpecFP results:

    True, it is a bit of an overstatement, but CFP2000 seems to be the
    exception rather than the norm. Many other tests have shown little to
    no improvement, with a number actually being slower on the Prescott
    rather than the Northwood. If all results reflected what we see in
    SPEC CPU2000 I don't think people would say much, but as it stands
    it's left more than a few people (myself included) wonder just what
    the heck all those extra transistors really bought them.

    >Intel D875PBZ motherboard (3.4 GHz, Pentium 4 processor with HT
    >Technology) 1308 1300 1 Mar-2004 Config
    >
    >Intel D875PBZ motherboard (AA-301) (3.4E GHz, Pentium 4 Processor with
    >HT Technology) 1485 1481 1 core, 1 chip, 1 core/chip (HT
    >[enabled)] Apr-2004
    >
    >That's a bigger bump than you get from going to the extreme edition at
    >the same frequency.

    Uhh.. really?

    Intel Corporation Intel D875PBZ motherboard (AA-301) (3.4 GHz,
    Pentium 4 Processor with HT Technology Extreme Edition)
    1548 1561

    Seems to me like the Extreme Edition is still a decent amount faster..

    >The 3.4E result is with HT on and the 3.4 result is with HT off. No
    >published way, so far as I can tell to sort out the effects of HT on vs.
    >HT off as compared to 3.4 vs. 3.4E.

    Tough call. I wouldn't imagine that it would help much given the
    single-threaded nature of SPEC CPU2000, but Intel is now turning HT on
    for all of their newest results, so I'm guessing they found some way
    to exploit it for a performance gain.

    Hmm, I just noticed that they have some results up for their new i925
    platform and the 3.6GHz P4E. They posted a rather respectable
    1627/1630 for this setup, faster than the 3.4GHz P4EE.

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
  24. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    In article <CzOVc.7587$LV1.7199@nwrddc02.gnilink.net>,
    "Raymond" <nospam@aly.net> writes:
    |>
    |> http://public.itrs.net/Files/2003ITRS/Home2003.htm
    |> http://www.intel.com/research/silicon/micron.htm
    |>
    |> Basically, the outlook looks quite good for the next 5+ years.

    Having looked at them, there are a lot of discrepancies. While
    I know next to nothing about the details of such technologies,
    I am fairly good at spotting inconsistencies. Try a few of the
    following:

    90 nm mass production in 2003? Demonstration versions only; ITRS
    correctly claims 2004 for 90 nm. Note that the extra year was from
    being able to get the process to produce working CPUs to the point
    where they could be produced economically and viably.

    Intel are quoting 65 nm for 2005. Well, I have this bridge for
    sale .... ITRS quite reasonably talk about 2007. Intel may well
    sell their first 65 nm CPUs on the open market in 2006, as they
    did with the 90 nm ones in 2003, but that doesn't mean that they
    will be in serious production.

    I looked at the ITRS lithography section and failed to find passive
    leakage as a major issue, though it may have been elsewhere. Note
    that it ISN'T just a case of preventing the power from increasing,
    but being able to REDUCE it. More compact devices means more of
    them in smaller spaces.


    Regards,
    Nick Maclaren.
  25. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    > >> The real question that no one at Intel seems to be
    > >> able to answer is how they managed to more than double the number of
    > >> transistors (vs. Northwood) and not have anything to show for it.
    > >>
    > >
    > >Nothing to show for it is perhaps an overstatement, unless I am
    > >misreading SpecFP results:
    >
    > True, it is a bit of an overstatement, but CFP2000 seems to be the
    > exception rather than the norm. Many other tests have shown little to
    > no improvement, with a number actually being slower on the Prescott
    > rather than the Northwood. If all results reflected what we see in
    > SPEC CPU2000 I don't think people would say much, but as it stands
    > it's left more than a few people (myself included) wonder just what
    > the heck all those extra transistors really bought them.

    Okay most the extra transitors brought them better performance in
    DOOM3.
    Unfortunately for the rest of the transistors I don't know and those
    extra transistors take more area than the already mentioned
    transistors.
    http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2149&p=4

    Jouni Osmala
    Helsinki University of Technology
  26. Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

    On 29 Aug 2004 10:15:38 -0700, josmala@cc.hut.fi (Jouni Osmala) wrote:
    >> True, it is a bit of an overstatement, but CFP2000 seems to be the
    >> exception rather than the norm. Many other tests have shown little to
    >> no improvement, with a number actually being slower on the Prescott
    >> rather than the Northwood. If all results reflected what we see in
    >> SPEC CPU2000 I don't think people would say much, but as it stands
    >> it's left more than a few people (myself included) wonder just what
    >> the heck all those extra transistors really bought them.
    >
    >Okay most the extra transitors brought them better performance in
    >DOOM3.
    >Unfortunately for the rest of the transistors I don't know and those
    >extra transistors take more area than the already mentioned
    >transistors.
    >http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2149&p=4

    On the other hand it's slower than the Extreme Edition, and if Intel
    had done a straight shrink of the P4EE down to a 90nm fab process they
    probably would have ended up with more or less the same die size as
    the P4 "Prescott".

    Certainly there are situations where the Prescott does beat the
    Northwood, but as mentioned above, there are also many tests that show
    no improvement and even a fair number that show the Prescott being
    slower. With a more than 100% increase in transistor count one would
    normally expect a MUCH more convincing sign of improvement.

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
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