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bus=100Hz (cpu to ram? or there and back?) Also PC2100 RAM..

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September 12, 2004 1:47:17 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.periphs.mainboard,comp.sys.ibm.pc.hardware.systems (More info?)

Say a bus, like an FSB=100MHz, 100 cycles a second.
also, the bus is 8 bytes in size.
Suppose the RAM is just normal SDR (single data ram) not DDR. and it's
'single channel' not 'dual channel'.

I dunno if in each cycle, the data on the bus travels
both ways or just one way.
I guess it's there(CPU->MEMORY) and back(MEMORY-->CPU)
in the bytes we talk about carrying.
(i'll just remind myself that the data moves on the bus, and the bus
doesn't move ;)  )

For a Write the data only need to travel 1 way. CPU-->RAM.
For a Read, a little stuff travels CPU-->RAM (which i'll cal 'the
request' then a load(the data) from RAM-->CPU
Since the request doesn't need 8 bytes, (as it carries the address to
read from, no data on the data lines) I could see how perhaps the
journey of CPU-->RAM for a READ is not included if we are counting how
many MB of data is transferred per cycle and per second.
But if we count how long it takes per c
but it would take twice as long to do a READ, surely?
Does it? (i'm sure that it's not like a car on the road where the
journey back home always seems to be quicker!)
And, if READ takes twice as long, then in that time, you could do
2 WRITES, so that would have a big effect on MB/cycle and MB/s

So that is why i'm puzzled as to whether, in 1 Hz, the data on the bus
goes both ways, or just one way. And - since writes require 1 way, and
reads 2 ways (by my reasoning). Then does MB/cycle and MB/second
measure MB read or MB written?
So is PC2100 DDR-SDRAM 2100MB/s reading? or writing?
Anonymous
a b à CPUs
September 12, 2004 10:20:55 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.periphs.mainboard,comp.sys.ibm.pc.hardware.systems (More info?)

On 11 Sep 2004 21:47:17 -0700, q_q_anonymous@yahoo.co.uk (Anon) wrote:

>Say a bus, like an FSB=100MHz, 100 cycles a second.
>also, the bus is 8 bytes in size.
>Suppose the RAM is just normal SDR (single data ram) not DDR. and it's
>'single channel' not 'dual channel'.
>
>I dunno if in each cycle, the data on the bus travels
>both ways or just one way.
>I guess it's there(CPU->MEMORY) and back(MEMORY-->CPU)
>in the bytes we talk about carrying.
>(i'll just remind myself that the data moves on the bus, and the bus
>doesn't move ;)  )
>
>For a Write the data only need to travel 1 way. CPU-->RAM.
>For a Read, a little stuff travels CPU-->RAM (which i'll cal 'the
>request' then a load(the data) from RAM-->CPU
>Since the request doesn't need 8 bytes, (as it carries the address to
>read from, no data on the data lines) I could see how perhaps the
>journey of CPU-->RAM for a READ is not included if we are counting how
>many MB of data is transferred per cycle and per second.
>But if we count how long it takes per c
>but it would take twice as long to do a READ, surely?
>Does it? (i'm sure that it's not like a car on the road where the
>journey back home always seems to be quicker!)
>And, if READ takes twice as long, then in that time, you could do
>2 WRITES, so that would have a big effect on MB/cycle and MB/s
>
>So that is why i'm puzzled as to whether, in 1 Hz, the data on the bus
>goes both ways, or just one way. And - since writes require 1 way, and
>reads 2 ways (by my reasoning). Then does MB/cycle and MB/second
>measure MB read or MB written?
>So is PC2100 DDR-SDRAM 2100MB/s reading? or writing?

Here's an animated illustration, originally supplied by Dave Wang, of the
signalling and data movement betwwen a PPro-PIII, chipset and SDRAM:
http://www.warthman.com/ex-ppro.htm. Yes, if you look at consecutive burst
cycles, you do have "info" in both directions on the memory bus but only on
the data and request/address lines of the bus.

There's no illustration of a Write cycle but you're correct that the data
and Write command request can be coincident with each other but there are
complications, e.g. if a Write follows a Read with both banks open, the
Write may have to wait a clock for the data bus to settle. With DDR-SDRAM
there are further complications with source clocked bus turn-around.
There's also the overhead of the Activate command and the Trcd for Writes
as well as Reads. There are lots of complex interactions, especially with
open banks, but the bottom line is that a series of back-to-back random
Writes should complete faster than a series of random Reads because you
save on the CAS latency with the Writes. Will you notice? I don't think
so.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??
!