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Anonymous
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December 16, 2004 1:11:55 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Chipset house SiS's director was interviewed by Digitimes recently. One
interesting that he said was that he's been encouraging AMD not to keep
integrating the memory controller into the processor.

> Q: Designing chipsets for K8 platform would appear to be easier because there is no need to incorporate a memory controller in the northbridge since it's integrated in the processor itself. Does that mean the role of the chipset itself and the chipset maker comes to be less important when we talk about the AMD platform?
>
> A: No, it doesn't. Moreover, I believe we have more experience than AMD in designing memory controllers. Actually, we'd like to see AMD stop putting the memory controller in the CPU. I approached AMD about this several times, but they have their own reasons for integrating the memory controller with the CPU.

Fabless once more – An interview with SiS director Nelson Lee
http://www.digitimes.com/mobos/a20041216PR202.html

Yousuf Khan
Anonymous
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December 16, 2004 1:11:56 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

> Yousuf Khan <bbbl67@ezrs.com> wrote:

>> SiS: Actually, we'd like to see AMD stop putting the memory controller
>> in the CPU.

Apart from the obvious self-interest (it eliminates the
northbridge chip market), what point might SiS being
trying to make here?

Seems like this public message might not be intended
for the public.

--
Regards, Bob Niland mailto:name@ispname.tld
http://www.access-one.com/rjn email4rjn AT yahoo DOT com
NOT speaking for any employer, client or Internet Service Provider.
Anonymous
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December 16, 2004 3:04:34 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Bob Niland wrote:
> Apart from the obvious self-interest (it eliminates the
> northbridge chip market), what point might SiS being
> trying to make here?
>
> Seems like this public message might not be intended
> for the public.
>

I could think of several reasons. The one which seems to make the most
sense to me is that having to continue to make Pentium 4 chipsets at the
same time as Athlon 64 chipsets, their two chipsets are quite different.
They don't get to save on not having to make a memory controller
anymore, since they still have to make Pentium 4 chipsets.

Yousuf Khan
Related resources
Anonymous
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December 16, 2004 4:42:55 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 15 Dec 2004 22:11:55 -0500, Yousuf Khan <bbbl67@ezrs.com>
wrote:

>Chipset house SiS's director was interviewed by Digitimes recently. One
>interesting that he said was that he's been encouraging AMD not to keep
>integrating the memory controller into the processor.
>
>> Q: Designing chipsets for K8 platform would appear to be easier because there is no need to incorporate a memory controller in the northbridge since it's integrated in the processor itself. Does that mean the role of the chipset itself and the chipset maker comes to be less important when we talk about the AMD platform?
>>
>> A: No, it doesn't. Moreover, I believe we have more experience than AMD in designing memory controllers. Actually, we'd like to see AMD stop putting the memory controller in the CPU. I approached AMD about this several times, but they have their own reasons for integrating the memory controller with the CPU.


One of SiS' main market is integrated video chipsets, and the on-die
memory controller of the Athlon64 is a bit of a hindrance for this.

That being said, SiS is barking up the wrong tree if they want AMD to
stop. Their best argument is that it will slightly slow performance
at the low-end of things with integrated video, where performance
doesn't mean much. On the flip side though, the integrated memory
controller offers tremendous performance advantage for high-end
systems with add-in video cards and where performance is important.

As for AMD vs. SiS memory controller designs, I'd take an AMD one any
day.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
December 16, 2004 7:16:33 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan <bbbl67@ezrs.com> wrote :

>> A: No, it doesn't. Moreover, I believe we have more experience
>> than AMD in designing memory controllers

yes, in designing ASS CHEAP SLOW memory controllers ....

Pozdrawiam.
--
RusH //
http://randki.o2.pl/profil.php?id_r=352019
Like ninjas, true hackers are shrouded in secrecy and mystery.
You may never know -- UNTIL IT'S TOO LATE.
Anonymous
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December 16, 2004 7:16:34 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

RusH wrote:
> Yousuf Khan <bbbl67@ezrs.com> wrote :
>
>
>>>A: No, it doesn't. Moreover, I believe we have more experience
>>>than AMD in designing memory controllers
>
>
> yes, in designing ASS CHEAP SLOW memory controllers ....

They were among the faster memory controllers in the early Athlon
Classic/Athlon XP days. And they didn't have the typical compatibility
problems that VIA typically gets when they push their performance too far.

Yousuf Khan
Anonymous
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December 16, 2004 7:35:51 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan <bbbl67@ezrs.com> wrote:
>> A: No, it doesn't. Moreover, I believe we have more experience
>> than AMD in designing memory controllers. Actually, we'd like
>> to see AMD stop putting the memory controller in the CPU. I
>> approached AMD about this several times, but they have their
>> own reasons for integrating the memory controller with the CPU.
>> Nelson Lee http://www.digitimes.com/mobos/a20041216PR202.html

He may have a small point. Lots of devices (esp AGP vidcards)
do BM-DMA. They're going to experience increased latency
going through the CPU integral MC. But that's probably better
than the CPU suffering the latency with a traditional Northbridge.

-- Robert
Anonymous
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a b } Memory
December 16, 2004 9:08:33 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Bob Niland wrote:
>> Yousuf Khan <bbbl67@ezrs.com> wrote:
>
>
>>> SiS: Actually, we'd like to see AMD stop putting the memory
>>> controller in the CPU.
>
>
> Apart from the obvious self-interest (it eliminates the
> northbridge chip market), what point might SiS being
> trying to make here?
>
> Seems like this public message might not be intended
> for the public.
>

The AMD64 processors do *not* have to use the built in memory
controller. There is nothing stopping SiS from building an
AMD64 chipset with its own memory controller - but they'll
have a hard time getting anyone to use such a chipset unless
they can demonstrate concrete advantages.
December 16, 2004 12:17:23 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan <bbbl67@ezrs.com> wrote :

> RusH wrote:
>> Yousuf Khan <bbbl67@ezrs.com> wrote :
>>
>>
>> yes, in designing ASS CHEAP SLOW memory controllers ....
>
> They were among the faster memory controllers in the early Athlon
> Classic/Athlon XP days. And they didn't have the typical
> compatibility problems that VIA typically gets when they push
> their performance too far.

I might be biased, i used to "work" on sis630, the slowest P3 ever.
Sandra showed Celeron 266 memory "performance" on a 133MHz CPU.

Pozdrawiam.
--
RusH //
http://randki.o2.pl/profil.php?id_r=352019
Like ninjas, true hackers are shrouded in secrecy and mystery.
You may never know -- UNTIL IT'S TOO LATE.
Anonymous
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a b } Memory
December 16, 2004 12:21:35 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

RusH <logistyka1@pf.pl> wrote:

>Yousuf Khan <bbbl67@ezrs.com> wrote :
>
>>> A: No, it doesn't. Moreover, I believe we have more experience
>>> than AMD in designing memory controllers
>
>yes, in designing ASS CHEAP SLOW memory controllers ....

Heh. SiS=brand X. I don't think I'd makes big decisions around what
they think is right...
December 16, 2004 5:19:24 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 15 Dec 2004 22:11:55 -0500, Yousuf Khan <bbbl67@ezrs.com>
wrote:

>Chipset house SiS's director was interviewed by Digitimes recently. One
>interesting that he said was that he's been encouraging AMD not to keep
>integrating the memory controller into the processor.
>
>> Q: Designing chipsets for K8 platform would appear to be easier because there is no need to incorporate a memory controller in the northbridge since it's integrated in the processor itself. Does that mean the role of the chipset itself and the chipset maker comes to be less important when we talk about the AMD platform?
>>
>> A: No, it doesn't. Moreover, I believe we have more experience than AMD in designing memory controllers. Actually, we'd like to see AMD stop putting the memory controller in the CPU. I approached AMD about this several times, but they have their own reasons for integrating the memory controller with the CPU.
>
>Fabless once more – An interview with SiS director Nelson Lee
>http://www.digitimes.com/mobos/a20041216PR202.html
>
> Yousuf Khan

If SIS thinks it can do better with their own memory controller in
northbridge, there's nothing that prevents them from doing so. K8
family of processors can access memory either through their own
integrated controller or through external memory controller as long as
it has hypertransport link. Case in point - dual Opty boards where
only CPU 0 accesses the memory directly, and CPU 1 goes through 0. I
doubt though that this would bring any benefits in terms of
performance. What it could do is making easier switch to different
type of memory (such as DDR2 when it comes up to speed - 667? 800?)
Anonymous
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a b } Memory
December 16, 2004 11:41:01 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

nobody@nowhere.net wrote:
> If SIS thinks it can do better with their own memory controller in
> northbridge, there's nothing that prevents them from doing so. K8
> family of processors can access memory either through their own
> integrated controller or through external memory controller as long as
> it has hypertransport link. Case in point - dual Opty boards where
> only CPU 0 accesses the memory directly, and CPU 1 goes through 0. I
> doubt though that this would bring any benefits in terms of
> performance. What it could do is making easier switch to different
> type of memory (such as DDR2 when it comes up to speed - 667? 800?)
>

Well, maybe they can do this, i.e. offer a DDR2 interface for the
DDR-only Athlon 64's. But from what I've heard, AMD is already ready
with the DDR2 circuitry in its chips -- they'll just lay dormant inside
while AMD transitions over to the next socket format (the one with over
1200 pins). So at best, it'll be a good short-term feature that SiS can
market to people who want to upgrade to DDR2 but don't want to give up
their older Athlon 64's.

Yousuf Khan
Anonymous
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December 17, 2004 2:20:05 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Tony Hill wrote:
> The simple fact of the matter is that integrated memory controllers
on
> CPU dies is the way to go. Everyone except Intel has already
> recognized that.

Well, actually Intel *has* recognized it now:

Intel to overhal its memory bus architecture
http://www.computerweekly.com/articles/article.asp?liAr...
Yousuf Khan
Anonymous
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a b } Memory
December 17, 2004 9:59:15 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On 17 Dec 2004 11:20:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:

>Tony Hill wrote:
>> The simple fact of the matter is that integrated memory controllers
>on
>> CPU dies is the way to go. Everyone except Intel has already
>> recognized that.
>
>Well, actually Intel *has* recognized it now:
>
>Intel to overhal its memory bus architecture
>http://www.computerweekly.com/articles/article.asp?liAr...
>Yousuf Khan

Hmmm, just what we were talking about two weeks ago:
cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??
Anonymous
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a b } Memory
December 18, 2004 2:53:21 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

George Macdonald wrote:
>>Well, actually Intel *has* recognized it now:
>>
>>Intel to overhal its memory bus architecture
>>http://www.computerweekly.com/articles/article.asp?liAr...
>>Yousuf Khan
>
>
> Hmmm, just what we were talking about two weeks ago:
> cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com.

Uh, what exactly is that a link to above?

Yousuf Khan
Anonymous
a b à CPUs
a b } Memory
December 18, 2004 2:57:42 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

RusH wrote:
> I might be biased, i used to "work" on sis630, the slowest P3 ever.
> Sandra showed Celeron 266 memory "performance" on a 133MHz CPU.

SiS used to be known for some cheap-ass performance. I can recall back
to the original Pentium days, I helped a friend obtain a Pentium 90
mobo, and then helped him return it too. It was horrible performance,
but had excellent features (except the features ran slowly). :-)

However, I later obtained an ECS K7S5A motherboard with the SiS 735
chipset, and it's still running this machine to this day. The most
long-lived motherboard I've had yet. And I had originally bought it
because it was cheap, so I wasn't expecting it to be too long lived. I
just assumed at the price I paid for it, I'll have recouped my
investment very quickly, even if it goes out after a year. Still running
4 years on.

Yousuf Khan
Anonymous
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a b } Memory
December 18, 2004 3:12:20 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Tony Hill wrote:
> One of SiS' main market is integrated video chipsets, and the on-die
> memory controller of the Athlon64 is a bit of a hindrance for this.
>
> That being said, SiS is barking up the wrong tree if they want AMD to
> stop. Their best argument is that it will slightly slow performance
> at the low-end of things with integrated video, where performance
> doesn't mean much. On the flip side though, the integrated memory
> controller offers tremendous performance advantage for high-end
> systems with add-in video cards and where performance is important.

I've never seen anybody play up the "my integrated video controller is
better than yours" hand.

You got integrated video? Dude, you're getting a video card (/any/ video
card).

Yousuf Khan
Anonymous
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a b } Memory
December 19, 2004 4:28:19 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sat, 18 Dec 2004 11:53:21 -0500, Yousuf Khan <bbbl67@ezrs.com> wrote:

>George Macdonald wrote:
>>>Well, actually Intel *has* recognized it now:
>>>
>>>Intel to overhal its memory bus architecture
>>>http://www.computerweekly.com/articles/article.asp?liAr...
>>>Yousuf Khan
>>
>>
>> Hmmm, just what we were talking about two weeks ago:
>> cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com.
>
>Uh, what exactly is that a link to above?

A Usenet Message ID - if your newsreader doesn't support it, sorry... but
you can plug it in at Google Groups.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??
Anonymous
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December 19, 2004 7:10:58 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On 17 Dec 2004 11:20:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:

>Tony Hill wrote:
>> The simple fact of the matter is that integrated memory controllers
>on
>> CPU dies is the way to go. Everyone except Intel has already
>> recognized that.
>
>Well, actually Intel *has* recognized it now:

Err.. have they?!?

>Intel to overhal its memory bus architecture
>http://www.computerweekly.com/articles/article.asp?liAr...
>Yousuf Khan

From this very link:

"Intel's current front-side system bus design should be able to keep
as many as four cores satisfied, depending on their frequency, said
Stephen Pawlowski, an Intel senior fellow"

Seems to me like Intel does NOT have any plans for an integrated
memory controller. In fact, that whole article is just more people
echoing what we've all been saying in this newsgroup for a little bit,
that sooner or later Intel HAS to integrate their memory controller if
they want to remain at all competitive. Still, in this article they
continue to sound like they're in denial. 4 cores off a front-side
bus design?! One only needs to look at just how poorly the 4
processor Xeon performs relative to the Opteron to realize that the
above-mention "Intel senior fellow" is smoking some wacky stuff.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
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December 19, 2004 6:01:29 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

George Macdonald wrote:
>>>Hmmm, just what we were talking about two weeks ago:
>>>cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com.
>>
>>Uh, what exactly is that a link to above?
>
>
> A Usenet Message ID - if your newsreader doesn't support it, sorry... but
> you can plug it in at Google Groups.

Just plugged it into Google Groups, and it just came up with this exact
same message with that message id in the body. Why not just post a
Google Groups link to the message?

Yousuf Khan
Anonymous
a b à CPUs
a b } Memory
December 19, 2004 9:46:29 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Tony Hill <hilla_nospam_20@yahoo.ca> wrote:

> Seems to me like Intel does NOT have any plans for an integrated
> memory controller. In fact, that whole article is just more people
> echoing what we've all been saying in this newsgroup for a little bit,
> that sooner or later Intel HAS to integrate their memory controller if
> they want to remain at all competitive. Still, in this article they
> continue to sound like they're in denial. 4 cores off a front-side
> bus design?! One only needs to look at just how poorly the 4
> processor Xeon performs relative to the Opteron to realize that the
> above-mention "Intel senior fellow" is smoking some wacky stuff.

4P Xeon's on the same FSB loads down the interconnect, and that limits
the datarate. 4P Xeon's are running at 400 Mbps while their 1P desktop
brethen are cranking at 800 Mbps going to 1066 Mbps. It would seem that
there is a significant bandwidth differential between the 4P/4S (4
processor, 4 socket) config and the 4P/1S config.






--
davewang202(at)yahoo(dot)com
Anonymous
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a b } Memory
December 20, 2004 7:45:46 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sun, 19 Dec 2004 15:01:29 -0500, Yousuf Khan <bbbl67@ezrs.com> wrote:

>George Macdonald wrote:
>>>>Hmmm, just what we were talking about two weeks ago:
>>>>cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com.
>>>
>>>Uh, what exactly is that a link to above?
>>
>>
>> A Usenet Message ID - if your newsreader doesn't support it, sorry... but
>> you can plug it in at Google Groups.
>
>Just plugged it into Google Groups, and it just came up with this exact
>same message with that message id in the body. Why not just post a
>Google Groups link to the message?

It *is* a Google Groups "link". No not as a search string - in Google
Advanced Groups Search, paste it into the Message ID box. I haven't even
looked at Thunderbird yet but Free Agent can use it directly within its own
message list.

If you must, here's the resulting msg:
http://groups-beta.google.com/group/comp.sys.ibm.pc.har...

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??
December 20, 2004 11:14:26 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"Robert Redelmeier" <redelm@ev1.net.invalid> wrote in message
news:Hg8wd.247$wi2.19@newssvr11.news.prodigy.com...
> Yousuf Khan <bbbl67@ezrs.com> wrote:
> >> A: No, it doesn't. Moreover, I believe we have more experience
> >> than AMD in designing memory controllers. Actually, we'd like
> >> to see AMD stop putting the memory controller in the CPU. I
> >> approached AMD about this several times, but they have their
> >> own reasons for integrating the memory controller with the CPU.
> >> Nelson Lee http://www.digitimes.com/mobos/a20041216PR202.html
>
> He may have a small point. Lots of devices (esp AGP vidcards)
> do BM-DMA. They're going to experience increased latency
> going through the CPU integral MC. But that's probably better
> than the CPU suffering the latency with a traditional Northbridge.
>

Why would you think so? The bus-master traffic has to be snooped
and snarfed anyway. In architectures with FSB is it done via
slow FSB, but with integrated MC it surely can be done faster.
Therefore, SiS has no point except that they might be hinting on some
general deficiency of AMD controllers, say, limited support for bigger
memory capacity, drive strength, future speeds, or newer memory
types.

- aap
Anonymous
a b à CPUs
a b } Memory
December 20, 2004 11:14:27 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Mon, 20 Dec 2004 08:14:26 GMT, "alexi"
<apredtechenski.no.spam@austin.rr.com> wrote:

>
>"Robert Redelmeier" <redelm@ev1.net.invalid> wrote in message
>news:Hg8wd.247$wi2.19@newssvr11.news.prodigy.com...
>> Yousuf Khan <bbbl67@ezrs.com> wrote:
>> >> A: No, it doesn't. Moreover, I believe we have more experience
>> >> than AMD in designing memory controllers. Actually, we'd like
>> >> to see AMD stop putting the memory controller in the CPU. I
>> >> approached AMD about this several times, but they have their
>> >> own reasons for integrating the memory controller with the CPU.
>> >> Nelson Lee http://www.digitimes.com/mobos/a20041216PR202.html
>>
>> He may have a small point. Lots of devices (esp AGP vidcards)
>> do BM-DMA. They're going to experience increased latency
>> going through the CPU integral MC. But that's probably better
>> than the CPU suffering the latency with a traditional Northbridge.
>>
>
>Why would you think so? The bus-master traffic has to be snooped
>and snarfed anyway.

It *is* an interesting question. There is bound to be some latency from
Hypertransport packet processing and the quoted 4GB/s (on the latest 1GHz
versions) each way seems to ignore that - latency figures would be nice.:-)
AGP traffic doesn't have to be snooped, not the bulk transfer stuff anyway,
and it's 2.1GB/s peak rate is well within HT's capacity. I'm not sure how
PCI-Express sits here with packet disassembly/reassembly between the two
and the peak rate for both at 4GB/s but for the data phase, Intel's MCH
would have to be faster in general for PCI-Express bulk video data... I'd
think. I assume that the 16-lane PCI-Express video data doesn't have to be
snooped?

> In architectures with FSB is it done via
>slow FSB, but with integrated MC it surely can be done faster.
>Therefore, SiS has no point except that they might be hinting on some
>general deficiency of AMD controllers, say, limited support for bigger
>memory capacity, drive strength, future speeds, or newer memory
>types.

The only thing I've seen is that the 2T timing which AMD suggests for large
memory seems to have quite a drastic effect on bandwidth - "non-scientific"
observation of a drop of ~1GB/s on socket 939 systems.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??
!