Intel finally has a Hypertransport competitor: CSI bus

[Guest]

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

The CSI bus is optimized for low latency when used as a cache
coherent processor bus in four-processor systems. However, it can also
be used to link up to 16 CPUs for the high-end X86 systems built by
OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without
cache coherency as a standard way to link north and south bridge chips
in a processor core logic set.

SiliconStrategies.com - Intel preps HyperTransport competitor for Xeon,
Itanium CPUs
http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=60404677&_requestid=325546

Yousuf Khan

 

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Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

On 2 Mar 2005 09:21:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:

>

The CSI bus is optimized for low latency when used as a cache
>coherent processor bus in four-processor systems. However, it can also
>be used to link up to 16 CPUs for the high-end X86 systems built by
>OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without
>cache coherency as a standard way to link north and south bridge chips
>in a processor core logic set.

>
>SiliconStrategies.com - Intel preps HyperTransport competitor for Xeon,
>Itanium CPUs
>http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=60404677&_requestid=325546
>
> Yousuf Khan

Comes complete with a measurable error rate, too...

 

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Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

daytripper wrote:
> On 2 Mar 2005 09:21:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:
>
>
>>

The CSI bus is optimized for low latency when used as a cache
>>coherent processor bus in four-processor systems. However, it can also
>>be used to link up to 16 CPUs for the high-end X86 systems built by
>>OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without
>>cache coherency as a standard way to link north and south bridge chips
>>in a processor core logic set.

>>
>>SiliconStrategies.com - Intel preps HyperTransport competitor for Xeon,
>>Itanium CPUs
>>http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=60404677&_requestid=325546
>>
>> Yousuf Khan
>
>
> Comes complete with a measurable error rate, too...

Where did you see something about CSI error rate?


del cecchi

 

[keith]

Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 02 Mar 2005 13:42:09 -0500, daytripper wrote:

> On 2 Mar 2005 09:21:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:
>
>>

The CSI bus is optimized for low latency when used as a cache
>>coherent processor bus in four-processor systems. However, it can also
>>be used to link up to 16 CPUs for the high-end X86 systems built by
>>OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without
>>cache coherency as a standard way to link north and south bridge chips
>>in a processor core logic set.

>>
>>SiliconStrategies.com - Intel preps HyperTransport competitor for Xeon,
>>Itanium CPUs
>>http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=60404677&_requestid=325546
>>
>> Yousuf Khan
>
> Comes complete with a measurable error rate, too...

Are they different for Miami and Las Vegas?

--
Keith

 

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On Wed, 02 Mar 2005 21:12:26 -0500, keith <krw@att.bizzzz> wrote:

>On Wed, 02 Mar 2005 13:42:09 -0500, daytripper wrote:
>
>> On 2 Mar 2005 09:21:05 -0800, "YKhan" <yjkhan@gmail.com> wrote:
>>
>>>

The CSI bus is optimized for low latency when used as a cache
>>>coherent processor bus in four-processor systems. However, it can also
>>>be used to link up to 16 CPUs for the high-end X86 systems built by
>>>OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without
>>>cache coherency as a standard way to link north and south bridge chips
>>>in a processor core logic set.

>>>
>>>SiliconStrategies.com - Intel preps HyperTransport competitor for Xeon,
>>>Itanium CPUs
>>>http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=60404677&_requestid=325546
>>>
>>> Yousuf Khan
>>
>> Comes complete with a measurable error rate, too...
>
>Are they different for Miami and Las Vegas?

Nah, I imagine the underlying technology will burp just as often no matter
where it is operated.

If basic strategy is to layer ECC and Retry on a link, is that enough of a
hint?

/daytripper ()

 

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Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips (More info?)

daytripper wrote:
>>>Comes complete with a measurable error rate, too...
>>
>>Are they different for Miami and Las Vegas?
>
>
> Nah, I imagine the underlying technology will burp just as often no matter
> where it is operated.
>
> If basic strategy is to layer ECC and Retry on a link, is that enough of a
> hint?

To me that is simply an indication that they intend this thing to work
even if a given link turn out to be less than perfect.

Even if error rates are in the 'probably none during the lifetime of the
equipment', I'd still like to include the capability to detect, correct,
and if needed retransmit, any actual failing packet.

The only real problem is that for very low error rates you have to have
some way to intentionally introduce them during testing, otherwise you
won't know that the correction/retransmit parts actually work.

Terje

--
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"