"Analysis of IBM's Hurricane x86 chipset"

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

There was a lot of interest about this in this newsgroup a while
ago, so here's a good read on the subject:

http://www.realworldtech.com/page.cfm?ArticleID=RWT042405213553

(Found this at http://www.aceshardware.com/)
5 answers Last reply
More about analysis hurricane chipset
  1. Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

    On Fri, 29 Apr 2005 16:51:45 GMT, Rob Stow <rob.stow@shaw.ca> wrote:

    >There was a lot of interest about this in this newsgroup a while
    >ago, so here's a good read on the subject:
    >
    >http://www.realworldtech.com/page.cfm?ArticleID=RWT042405213553
    >
    >(Found this at http://www.aceshardware.com/)

    If anyone is interested in some comparative benchmarks, there are SPEC
    CINT_rate numbers up now for both this IBM x366 system using this
    Hurricane chipset and Dell's Poweredge 6850 using Intel's new E8500
    chipset.

    Here's a few 4-processor systems for SPEC CINT2000 Rate:

    Dell Poweredge 6850, 3.33GHz/8MB L3: 70.8 / 72.2 (base/peak)
    http://www.spec.org/cpu2000/results/res2005q2/cpu2000-20050321-03933.html

    Dell Poweredge 6850, 3.66GHz/0MB L3: 53.4 / 56.4
    http://www.spec.org/cpu2000/results/res2005q2/cpu2000-20050321-03923.html

    IBM x366, 3.66GHz/0MB L3: 67.2 / 67.5
    http://www.spec.org/cpu2000/results/res2005q2/cpu2000-20050324-03943.html


    As you can see, using like CPUs results in the IBM chipset being MUCH
    faster than the Intel one, however IBM's claim that their chipset
    eliminates the need for large L3 caches on Xeons doesn't quite hold
    water here. Sure, they do get pretty close to the large L3 cache Dell
    systems, but don't quite match them despite having a clock speed
    advantage.


    Ohh, another quick (somewhat unrelated) benchmark for those that are
    more interested TPC stuff:

    http://www.tpc.org/tpcc/results/tpcc_result_detail.asp?id=105042002

    First TPC-C benchmarks I've seen of a dual-core x86 processor, and
    they're fairly impressive, especially on the $/tpmC scale. It manages
    to top IBM's recent entry for their x366 server that was previously
    the fastest 4-Processor (and by "processor" I mean "socket" here) x86
    system. In fact, only IBM's Power5-based p570 server is faster with 4
    "processors" (here IBM and AMD are defining/pricing "processor"
    differently).

    I still haven't seen any 4P servers using Intel's new E8500 chipset on
    TPC, so we'll have to wait a bit longer to see how it compares to the
    X3 chipset on that one.

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
  2. Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

    On Sat, 30 Apr 2005 14:36:45 -0400, Tony Hill
    <hilla_nospam_20@yahoo.ca> wrote:


    >
    >As you can see, using like CPUs results in the IBM chipset being MUCH
    >faster than the Intel one, however IBM's claim that their chipset
    >eliminates the need for large L3 caches on Xeons doesn't quite hold
    >water here. Sure, they do get pretty close to the large L3 cache Dell
    >systems, but don't quite match them despite having a clock speed
    >advantage.
    >

    The magic I could identify, reading _very_ quickly through the
    extremetech article, was caching lines from another 4P node in memory
    local to a node. That is to say, multiple node systems use main
    memory to cache lines from other nodes. That's an advantage that
    would not show up, of course, in a single-node 4P system.

    RM
  3. Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

    > >As you can see, using like CPUs results in the IBM chipset being
    MUCH
    > >faster than the Intel one, however IBM's claim that their chipset
    > >eliminates the need for large L3 caches on Xeons doesn't quite hold
    > >water here. Sure, they do get pretty close to the large L3 cache
    Dell
    > >systems, but don't quite match them despite having a clock speed
    > >advantage.
    > >
    >
    > The magic I could identify, reading _very_ quickly through the
    > extremetech article, was caching lines from another 4P node in memory
    > local to a node. That is to say, multiple node systems use main
    > memory to cache lines from other nodes. That's an advantage that
    > would not show up, of course, in a single-node 4P system.

    That is right. The X3 has a virtual L4 which caches data from remote
    nodes (similar to HORUS' RDC, but using main memory). See my article
    at RWT for more details.

    Can I get a pointer to the Extreme tech article?

    David
  4. Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

    I'd happily supply a link to an extremetech article, if such a thing
    existed. As it is there is only the realworldtech article, which I
    misidentified. That is purely a function of the workings of my gray
    matter. I can't even blame the failing on age, as I have been doing
    such things for as long as I can remember. Sorry.

    RM
  5. Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

    rbmyers...@gmail.com wrote:
    > I'd happily supply a link to an extremetech article, if such a thing
    > existed. As it is there is only the realworldtech article, which I
    > misidentified. That is purely a function of the workings of my gray
    > matter. I can't even blame the failing on age, as I have been doing
    > such things for as long as I can remember. Sorry.
    >
    > RM

    Ah, well then, it looks like I'm all clear. You always have to worry
    about those competitors : )

    David
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