Intel will integrate the memory controller, and then some

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Intel strives for increased integration in future chips | InfoWorld |
News | 2005-04-29 | By Tom Krazit, IDG News Service
http://www.infoworld.com/article/0 [...] tes_1.html

Yousuf Khan

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

dawg wrote:
> Intel playing catch-up.
>
>

It seems about par for the course in recent times.

> Analysts and customers have been urging Intel to move away from its front-side bus design with the advent of multicore processors. In Intel's current chips, the interaction between the processor and a system's memory bank is handled by a memory controller located on the chipset that feeds data to the processor at various speeds ranging from 400MHz to 1066MHz, depending on the chip. This design has served the company well for many years, but as chips start to take advantage of multiple processing units, they require increased amounts of memory bandwidth in order to perform to their true potential.
>

Looks like nobody is even attempting claim the advantages of the
front-side bus architecture anymore.

Yousuf Khan