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AMD Pacifica virtualization technology specs released

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Anonymous
a b à CPUs
May 25, 2005 2:41:51 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

The specs for Pacifica have been released, which is AMD's answer to
Intel's Vanderpool virtualization.

According to this overview, there seems to be only two instructions
added to the regular x86 stack, which is VMRUN and VMCALL. Another
interesting new idea they've incorporated is is a "Paged Real Mode". So
it looks like they will be able to virtualize everything from 64-bit
OSes down to ancient 16-bit OSes.

Here's their overview Powerpoint:

http://search.amd.com/cs.html?url=http%3A//enterprise.a...||+pacifica,+|+language%3Aen&col=idx1&n=2
or,
http://tinyurl.com/7e8de

Yousuf Khan
Anonymous
a b à CPUs
May 26, 2005 9:03:06 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Well, I've found even more details about Pacifica (PT), as well as
Vanderpool (VT). One thing that's different between VT and PT is that
PT supports the virtualization of Real Mode (RM) and Non-Paged
Protected Mode (NPPM), but VT doesn't. Now RM & NPPM are two of the
most elderly machine states on x86 hardware. RM is where good old
MS-DOS used to run, while NPPM is where OS/2 1.x, Xenix, Windows 2.x
(286), and Windows 3.x in "Standard Mode" used to run. Not sure if any
of this extra functionality is actually useful in the real world
anymore, but in any case it's a more complete implementation.

Intel's documentation states that it expects the Hypervisor software to
emulate these modes for it:

Quote:
CR0.PE and CR0.PG restrictions imply that VMX operation is
supported only in paged protected mode (including IA-32e mode).
Therefore, guest software cannot be run in unpaged protected mode or in
real-address mode. If a VMM is to support guest software that expects
to run in unpaged protected mode or in real-address mode, the VMM must
support emulation of these modes. A VMM can use "identity" page
tables to emulate unpaged protected mode and can use virtual-8086 mode
as part of a strategy to emulate real-address mode.


I haven't gone through the PDF's in enough detail to determine whether
their implementations are just copies of each other with some names
changed but the opcodes remaining the same, or not.

Here's the links to the technical-spec PDF's:

AMD: http://tinyurl.com/9a8ys
<http://www.amd.com/us-en/assets/content_type/white_pape...;

Intel: http://tinyurl.com/8lbtj
<ftp://download.intel.com/technology/computing/vptech/C9...;
!