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Question about virtual machines--Apple on Intel

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Anonymous
a b à CPUs
June 7, 2005 12:35:34 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Greetings!

Well, somebody gets it:

http://www.eweek.com/article2/0,1759,1824810,00.asp

"Apple's Intel Desktop Move Threatens Linux Desktop, Longhorn"

I doubt seriously if OS X threatens Linux; Linux does and awfully good
job of marginalizing itself as a desktop OS. Windows is another story.


OS X will be a commercially-supported, BSD-based OS that runs on x86,
has a good user interface, and isn't loaded down with Gatesisms, such
as the tentacles of Internet Explorer growing into the innards of the
OS like something from a Sci-Fi movie.

I truly think Intel and Apple have a little more in mind than that
measly 3% of the market, and I'll bet I'm not the only one thinking it
might be payback time for Chairman Bill.

The Windows ace is hardware support. I assume Apple and Intel are
right now gathering in the sheaves of peripheral manufacturers to get
those device drivers written.

Then there is the existing software base, which brings me to my
question about virtual machines:

<quote>

OK, so you will be able to run legacy PowerPC applications on x86 PCs
with "dynamic binary translation." I've seen this kind of emulation
many times before. Even the best-Digital's FX!32 translator for the
Alpha a few years back for my money-doesn't give you much bang for
your processor buck.

See Special Report: Mac OS X in the EnterpriseOn the other hand, if
Apple, with some help from Intel, manages to get Mac OS X running with
VT (Virtualization Technology), all bets on performance are off.

VT is still a work in progress, but it's built on technology from
VMWare, and that company has already shown with products like VM
Workstation 5 that it knows how to build virtual machines that don't
sacrifice performance for compatibility.

</quote>

Ermph? That seems to imply that VT has something to do with the
efficiency of emulating, say, PowerPC on x86. I thought that VT just
made it easier to trap privileged instructions and to hide the overhead
of one OS running as the guest of another. You still have to run an
emulator if the ISA isn't native, and the emulator is still just as
inefficient. What is he trying to say, anyway?

RM
Anonymous
a b à CPUs
June 7, 2005 4:22:28 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

rbmyersusa@gmail.com wrote:
> VT is still a work in progress, but it's built on technology from
> VMWare, and that company has already shown with products like VM
> Workstation 5 that it knows how to build virtual machines that don't
> sacrifice performance for compatibility.
>
> </quote>
>
> Ermph? That seems to imply that VT has something to do with the
> efficiency of emulating, say, PowerPC on x86. I thought that VT just
> made it easier to trap privileged instructions and to hide the overhead
> of one OS running as the guest of another. You still have to run an
> emulator if the ISA isn't native, and the emulator is still just as
> inefficient. What is he trying to say, anyway?

Yeah yet another technology reporter that has managed to misinterpret
the purpose of a technology. Seems to happen quite rarely, but it
happens. :-)

VMWare "knows how to build virtual machines that don't sacrifice
performance" because it's very easy to emulate x86 instructions on x86
hardware itself. Emulation of one instruction set on another is a
different technological territory.

Yousuf Khan
June 8, 2005 12:06:34 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Tue, 07 Jun 2005 12:22:28 -0700, YKhan wrote:

> rbmyersusa@gmail.com wrote:
>> VT is still a work in progress, but it's built on technology from
>> VMWare, and that company has already shown with products like VM
>> Workstation 5 that it knows how to build virtual machines that don't
>> sacrifice performance for compatibility.
>>
>> </quote>
>>
>> Ermph? That seems to imply that VT has something to do with the
>> efficiency of emulating, say, PowerPC on x86. I thought that VT just
>> made it easier to trap privileged instructions and to hide the overhead
>> of one OS running as the guest of another. You still have to run an
>> emulator if the ISA isn't native, and the emulator is still just as
>> inefficient. What is he trying to say, anyway?
>
> Yeah yet another technology reporter that has managed to misinterpret
> the purpose of a technology. Seems to happen quite rarely, but it
> happens. :-)
>
> VMWare "knows how to build virtual machines that don't sacrifice
> performance" because it's very easy to emulate x86 instructions on x86
> hardware itself. Emulation of one instruction set on another is a
> different technological territory.

I'm quite interested in seeing how one emulates a PPC on x86 (without
tanking performance). They are *quite* different. Think about all the
'dot' instructions in PPC (and related CRs), not to mention the lack of a
stack. This is going to be interesting.

--
Keith
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Anonymous
a b à CPUs
June 8, 2005 12:50:58 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

keith wrote:
> I'm quite interested in seeing how one emulates a PPC on x86 (without
> tanking performance). They are *quite* different. Think about all the
> 'dot' instructions in PPC (and related CRs), not to mention the lack of a
> stack. This is going to be interesting.
>

It doesn't have a stack? What do they use? Register windows like on Sparc?

Yousuf Khan
June 9, 2005 2:06:35 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Tue, 07 Jun 2005 20:50:58 -0400, Yousuf Khan wrote:

> keith wrote:
>> I'm quite interested in seeing how one emulates a PPC on x86 (without
>> tanking performance). They are *quite* different. Think about all the
>> 'dot' instructions in PPC (and related CRs), not to mention the lack of a
>> stack. This is going to be interesting.
>>
>
> It doesn't have a stack?

No.

> What do they use?

For what?

Subroutine calls use the link register to store the address of the next
instruction (LK=1 in any branch instruction saves the return address
into link register). The return restores the link register to the
"Instruction Address Register" (which doesn't really exist ;) .

Interrupts use the Save/Restore Registers (SRR0/1) to save the address
of the return (which may be the current or next instruction) and the
Machine State Register.

Parameters are passed on your own stack, if you so choose.

> Register windows like on Sparc?

We're not talking Itanic here! ;-)

--
Keith
!