Intel embarrassed by own report

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

One of Intel's researchers published a whitepaper concluding that the
smaller chips get, the more errors they will be susceptible to. That
however does make the pursuit of Moore's Law questionable. Also makes
Intel's bragging to the press that it's months ahead of the competition
in moving to 65-nm not so enviable.

Intel back peddles on breaking chips theory - vnunet.com
http://www.vnunet.com/vnunet/news/2138064/intel-retracts-breaking-chips

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

"Yousuf Khan" <bbbl67@ezrs.com> wrote in message
news:be6se.7244$yU.552272@news20.bellglobal.com...

> One of Intel's researchers published a whitepaper concluding that the
> smaller chips get, the more errors they will be susceptible to. That
> however does make the pursuit of Moore's Law questionable. Also makes
> Intel's bragging to the press that it's months ahead of the competition in
> moving to 65-nm not so enviable.

I learned in college that as chips got smaller, they'd get faster to a
point. Then they would get slower, less reliable, and run hotter. My
professor doubted that chips would ever get below 125nm. He also showed me a
proof that 20,000 bps was over the limit possible over a conventional phone
line.

It wasn't that he was an idiot. It's that he couldn't anticipate future
discovery. Of course we never know how the next limit will be broken. If we
did, it wouldn't be a limit. But the limit breakers have always come. On
time.

DS

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On Wed, 15 Jun 2005 22:06:22 -0700, "David Schwartz" <davids@webmaster.com>
wrote:

>
>"Yousuf Khan" <bbbl67@ezrs.com> wrote in message
>news:be6se.7244$yU.552272@news20.bellglobal.com...
>
>> One of Intel's researchers published a whitepaper concluding that the
>> smaller chips get, the more errors they will be susceptible to. That
>> however does make the pursuit of Moore's Law questionable. Also makes
>> Intel's bragging to the press that it's months ahead of the competition in
>> moving to 65-nm not so enviable.
>
> I learned in college that as chips got smaller, they'd get faster to a
>point. Then they would get slower, less reliable, and run hotter. My
>professor doubted that chips would ever get below 125nm. He also showed me a
>proof that 20,000 bps was over the limit possible over a conventional phone
>line.
>
> It wasn't that he was an idiot. It's that he couldn't anticipate future
>discovery. Of course we never know how the next limit will be broken. If we
>did, it wouldn't be a limit. But the limit breakers have always come. On
>time.

And yet the DOD already has its own "flexible fab" to manufacture chips
which still work for them:
http://www.reed-electronics.com/electronicnews/article/CA608194.html and
"DMEA has recently analyzed a small sample of the latest semiconductors and
the robustness tests resulted in 100% failure..." Of course part of the
reasons for producing old chips is so they don't have to rewrite their
software but the failures are real. After the military, who's next?

--
Rgds, George Macdonald

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

George Macdonald wrote:
> On Wed, 15 Jun 2005 22:06:22 -0700, "David Schwartz" <davids@webmaster.com>
> wrote:
>
> >
> >"Yousuf Khan" <bbbl67@ezrs.com> wrote in message
> >news:be6se.7244$yU.552272@news20.bellglobal.com...
> >
> >> One of Intel's researchers published a whitepaper concluding that the
> >> smaller chips get, the more errors they will be susceptible to. That
> >> however does make the pursuit of Moore's Law questionable. Also makes
> >> Intel's bragging to the press that it's months ahead of the competition in
> >> moving to 65-nm not so enviable.
> >
> > I learned in college that as chips got smaller, they'd get faster to a
> >point. Then they would get slower, less reliable, and run hotter. My
> >professor doubted that chips would ever get below 125nm. He also showed me a
> >proof that 20,000 bps was over the limit possible over a conventional phone
> >line.
> >
> > It wasn't that he was an idiot. It's that he couldn't anticipate future
> >discovery. Of course we never know how the next limit will be broken. If we
> >did, it wouldn't be a limit. But the limit breakers have always come. On
> >time.
>
> And yet the DOD already has its own "flexible fab" to manufacture chips
> which still work for them:
> http://www.reed-electronics.com/electronicnews/article/CA608194.html and
> "DMEA has recently analyzed a small sample of the latest semiconductors and
> the robustness tests resulted in 100% failure..." Of course part of the
> reasons for producing old chips is so they don't have to rewrite their
> software but the failures are real. After the military, who's next?
>
Electromigation doesn't seem to be much on the radar--yet. What
happens when there are only a handful of dopant atoms in a gate? A few
dopant atoms migrate, and the electrical properties of the gate change
noticeably. If it's not an important effect, it will only be because
leakage has killed scaling before it can become important.

RM

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

David Schwartz wrote:
> "Yousuf Khan" <bbbl67@ezrs.com> wrote in message
> news:be6se.7244$yU.552272@news20.bellglobal.com...
>
>
>>One of Intel's researchers published a whitepaper concluding that the
>>smaller chips get, the more errors they will be susceptible to. That
>>however does make the pursuit of Moore's Law questionable. Also makes
>>Intel's bragging to the press that it's months ahead of the competition in
>>moving to 65-nm not so enviable.
>
>
> I learned in college that as chips got smaller, they'd get faster to a
> point. Then they would get slower, less reliable, and run hotter. My
> professor doubted that chips would ever get below 125nm. He also showed me a
> proof that 20,000 bps was over the limit possible over a conventional phone
> line.
>
> It wasn't that he was an idiot. It's that he couldn't anticipate future
> discovery. Of course we never know how the next limit will be broken. If we
> did, it wouldn't be a limit. But the limit breakers have always come. On
> time.
>
> DS
>
>
The limit on a phone line was defined by a guy named Shannon. I would
like to think the above professor had heard of him. Now the professor
might not have concieved of the advances that new coding techniques and
massive ammounts of cheap transistors have made possible but the limit
is there, defined by shannon.

del cecchi

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

rbmyersusa@gmail.com wrote:
> George Macdonald wrote:
>
>>On Wed, 15 Jun 2005 22:06:22 -0700, "David Schwartz" <davids@webmaster.com>
>>wrote:
>>
>>
>>>"Yousuf Khan" <bbbl67@ezrs.com> wrote in message
>>>news:be6se.7244$yU.552272@news20.bellglobal.com...
>>>
>>>
>>>>One of Intel's researchers published a whitepaper concluding that the
>>>>smaller chips get, the more errors they will be susceptible to. That
>>>>however does make the pursuit of Moore's Law questionable. Also makes
>>>>Intel's bragging to the press that it's months ahead of the competition in
>>>>moving to 65-nm not so enviable.
>>>
>>> I learned in college that as chips got smaller, they'd get faster to a
>>>point. Then they would get slower, less reliable, and run hotter. My
>>>professor doubted that chips would ever get below 125nm. He also showed me a
>>>proof that 20,000 bps was over the limit possible over a conventional phone
>>>line.
>>>
>>> It wasn't that he was an idiot. It's that he couldn't anticipate future
>>>discovery. Of course we never know how the next limit will be broken. If we
>>>did, it wouldn't be a limit. But the limit breakers have always come. On
>>>time.
>>
>>And yet the DOD already has its own "flexible fab" to manufacture chips
>>which still work for them:
>>http://www.reed-electronics.com/electronicnews/article/CA608194.html and
>>"DMEA has recently analyzed a small sample of the latest semiconductors and
>>the robustness tests resulted in 100% failure..." Of course part of the
>>reasons for producing old chips is so they don't have to rewrite their
>>software but the failures are real. After the military, who's next?
>>
>
> Electromigation doesn't seem to be much on the radar--yet. What
> happens when there are only a handful of dopant atoms in a gate? A few
> dopant atoms migrate, and the electrical properties of the gate change
> noticeably. If it's not an important effect, it will only be because
> leakage has killed scaling before it can become important.
>
> RM
>
Electromigration has been on the radar since more years than I want
think about. For a recent example, consider the transition from
Aluminium to Copper. Resistance decrease was nice. EM limit increase
was way nicer.

And did you notice that some brilliant outfit came out with a
statistical timing analysis program for timing chip designs?

del cecchi

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Del Cecchi wrote:

>
> And did you notice that some brilliant outfit came out with a
> statistical timing analysis program for timing chip designs?
>

As you know, I try to keep track of everything under the sun, but I
missed this one. Can you suggest a link?

RM

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On Wed, 15 Jun 2005 23:20:30 -0400, Yousuf Khan <bbbl67@ezrs.com> wrote:

>One of Intel's researchers published a whitepaper concluding that the
>smaller chips get, the more errors they will be susceptible to. That
>however does make the pursuit of Moore's Law questionable. Also makes
>Intel's bragging to the press that it's months ahead of the competition
>in moving to 65-nm not so enviable.
>
>Intel back peddles on breaking chips theory - vnunet.com
>http://www.vnunet.com/vnunet/news/2138064/intel-retracts-breaking-chips
>
> Yousuf Khan

<shameless plug alert>

My latest baby arrived on the showroom floor...

http://www.stratus.com/news/2005/20050606.htm

Our VP immediately cobbled together a press release referencing the Intel
white papers (there's a related Intel document out there) explaining why the
[alleged] trend should lead 24/7 mission-critical apps to our front door...

/daytripper (You got failure rate issues? We got solutions. Bring $$$ ;-)

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips Del Cecchi <cecchinospam@us.ibm.com> wrote:
> The limit on a phone line was defined by a guy named Shannon.
> I would like to think the above professor had heard of him.
> Now the professor might not have concieved of the advances

The real problem is that "average" SNR vs MHz graphs are
not commonly available for most media, including various grades
of phone lines or interstellar transmission (SETI).

Shannon's Limit takes [usually missing] data to apply.
The only common case where the data is available is from
Cat5+ cable certifications.

-- Robert

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

Robert Redelmeier wrote:
> In comp.sys.ibm.pc.hardware.chips Del Cecchi <cecchinospam@us.ibm.com> wrote:
>
>>The limit on a phone line was defined by a guy named Shannon.
>>I would like to think the above professor had heard of him.
>>Now the professor might not have concieved of the advances
>
>
> The real problem is that "average" SNR vs MHz graphs are
> not commonly available for most media, including various grades
> of phone lines or interstellar transmission (SETI).
>
> Shannon's Limit takes [usually missing] data to apply.
> The only common case where the data is available is from
> Cat5+ cable certifications.
>
> -- Robert
>
Then those guys doing DSL must have hacked the phone company or been
shooting in the dark... Or been reading BSTJ, or maybe bought a spool
of phone wire and layed it out in the back yard and done some
measurements. Sigh.

del cecchi

 

[keith]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Thu, 16 Jun 2005 15:09:06 -0700, rbmyersusa wrote:

> Del Cecchi wrote:
>
>>
>> And did you notice that some brilliant outfit came out with a
>> statistical timing analysis program for timing chip designs?
>>
>
> As you know, I try to keep track of everything under the sun, but I
> missed this one. Can you suggest a link?

Web search tools are wunnerful things:

http://www-03.ibm.com/technology/news/2005/060305statisticaltiming.shtml

--
Keith

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

David Schwartz wrote:
> "Yousuf Khan" <bbbl67@ezrs.com> wrote in message
> news:be6se.7244$yU.552272@news20.bellglobal.com...
>
>
>>One of Intel's researchers published a whitepaper concluding that the
>>smaller chips get, the more errors they will be susceptible to. That
>>however does make the pursuit of Moore's Law questionable. Also makes
>>Intel's bragging to the press that it's months ahead of the competition in
>>moving to 65-nm not so enviable.
>
>
> I learned in college that as chips got smaller, they'd get faster to a
> point. Then they would get slower, less reliable, and run hotter. My
> professor doubted that chips would ever get below 125nm. He also showed me a
> proof that 20,000 bps was over the limit possible over a conventional phone
> line.
>
> It wasn't that he was an idiot. It's that he couldn't anticipate future
> discovery. Of course we never know how the next limit will be broken. If we
> did, it wouldn't be a limit. But the limit breakers have always come. On
> time.

Actually I believe the real limit of small was defined back in a
DATAMATION article in the mid to late 60's. When traces drop below a
certain size, they stop conducting reliably. The real explanation lies
in a pile of quantum physics equations, I believe the layman's
explanation was "you drop an electron in one end and it may not come out
the other." Which is dreadfully inexact but easy to understand.

In any case the limit was some 15 (from memory) orders of magnitude
below the fabs of the day, and I don't think we're anywhere near that.

People are muttering that diamond substrate will be the solution, and
perhaps for heat it will, but for leakage?

--
bill davidsen
SBC/Prodigy Yorktown Heights NY data center
http://newsgroups.news.prodigy.com

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips Del Cecchi <cecchinospam@us.ibm.com> wrote:
> Then those guys doing DSL must have hacked the phone company
> or been shooting in the dark... Or been reading BSTJ, or maybe
> bought a spool of phone wire and layed it out in the back yard
> and done some measurements. Sigh.

They probably did all of this and more (field measurements of local
loops in the MHz range to understand impedence discontinuities).

-- Robert

 

[keith]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On Fri, 17 Jun 2005 01:35:50 +0000, Robert Redelmeier wrote:

> In comp.sys.ibm.pc.hardware.chips Del Cecchi <cecchinospam@us.ibm.com> wrote:
>> Then those guys doing DSL must have hacked the phone company
>> or been shooting in the dark... Or been reading BSTJ, or maybe
>> bought a spool of phone wire and layed it out in the back yard
>> and done some measurements. Sigh.
>
> They probably did all of this and more (field measurements of local
> loops in the MHz range to understand impedence discontinuities).

Discontinuities? PLease. The fact is that the local loop has becoem far
quieter than in years past (and likely to get even more so as people ditch
wires). The gain isn't because of some new magic, but because the S/N
ratio is better than what was expected. ...not to mention that the "last
mile" isn't twenty miles these days.

--
Keith

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

"Robert Redelmeier" <redelm@ev1.net.invalid> wrote in message
news:RUkse.1759$Nz2.70@newssvr11.news.prodigy.com...
> In comp.sys.ibm.pc.hardware.chips Del Cecchi <cecchinospam@us.ibm.com>
> wrote:
>> The limit on a phone line was defined by a guy named Shannon.
>> I would like to think the above professor had heard of him.
>> Now the professor might not have concieved of the advances
>
> The real problem is that "average" SNR vs MHz graphs are
> not commonly available for most media, including various grades
> of phone lines or interstellar transmission (SETI).

For phone lines see BSTJ, lots info ...

> Shannon's Limit takes [usually missing] data to apply.
> The only common case where the data is available is from
> Cat5+ cable certifications.



--

... Hank

http://home.earthlink.net/~horedson
http://home.earthlink.net/~w0rli

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips Hank Oredson <horedson@earthlink.net> wrote:
> For phone lines see BSTJ, lots info ...

In the MHz for subscriber loop? Maybe for inter-office
trunking before it was mostly replaced by fiber.

-- Robert

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips keith <krw@att.bizzzz> wrote:
> Discontinuities? PLease. The fact is that the local loop
> has becoem far quieter than in years past

New or rewired loops, yes. I'm not sure how old loops
magically improve

But there still are discontinuities at splices. Maybe
not much with the newer ones, but every little bit hurts,
especially at higher frequencies.


> (and likely to get even more so as people ditch wires).

I take that to mean bury. Yes. I worry a little the
aerial messenger could form a notch filter much like that
demo of uniform stapling coax ruining TV. Of course nothing
that would affect voice freqs.

> The gain isn't because of some new magic, but because the
> S/N ratio is better than what was expected. ...not to
> mention that the "last mile" isn't twenty miles these days.

Agreed. RTs are installed more often, but many city dwellers
are on shorter but older loops.

-- Robert

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On 16 Jun 2005 12:30:54 -0700, rbmyersusa@gmail.com wrote:

>George Macdonald wrote:
>> On Wed, 15 Jun 2005 22:06:22 -0700, "David Schwartz" <davids@webmaster.com>
>> wrote:
>>
>> >
>> >"Yousuf Khan" <bbbl67@ezrs.com> wrote in message
>> >news:be6se.7244$yU.552272@news20.bellglobal.com...
>> >
>> >> One of Intel's researchers published a whitepaper concluding that the
>> >> smaller chips get, the more errors they will be susceptible to. That
>> >> however does make the pursuit of Moore's Law questionable. Also makes
>> >> Intel's bragging to the press that it's months ahead of the competition in
>> >> moving to 65-nm not so enviable.
>> >
>> > I learned in college that as chips got smaller, they'd get faster to a
>> >point. Then they would get slower, less reliable, and run hotter. My
>> >professor doubted that chips would ever get below 125nm. He also showed me a
>> >proof that 20,000 bps was over the limit possible over a conventional phone
>> >line.
>> >
>> > It wasn't that he was an idiot. It's that he couldn't anticipate future
>> >discovery. Of course we never know how the next limit will be broken. If we
>> >did, it wouldn't be a limit. But the limit breakers have always come. On
>> >time.
>>
>> And yet the DOD already has its own "flexible fab" to manufacture chips
>> which still work for them:
>> http://www.reed-electronics.com/electronicnews/article/CA608194.html and
>> "DMEA has recently analyzed a small sample of the latest semiconductors and
>> the robustness tests resulted in 100% failure..." Of course part of the
>> reasons for producing old chips is so they don't have to rewrite their
>> software but the failures are real. After the military, who's next?
>>
>Electromigation doesn't seem to be much on the radar--yet. What
>happens when there are only a handful of dopant atoms in a gate? A few
>dopant atoms migrate, and the electrical properties of the gate change
>noticeably. If it's not an important effect, it will only be because
>leakage has killed scaling before it can become important.

I'd sure like to see Mr. Gaugler's "photographic evidence" before betting
the farm. Let's hope it gets published on-line.

--
Rgds, George Macdonald

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

<rbmyersusa@gmail.com> wrote in message
news:1118959746.898811.150630@f14g2000cwb.googlegroups.com...
> Del Cecchi wrote:
>
>>
>> And did you notice that some brilliant outfit came out with a
>> statistical timing analysis program for timing chip designs?
>>
>
> As you know, I try to keep track of everything under the sun, but I
> missed this one. Can you suggest a link?
>
> RM
>
Why, certainly.

http://www.ibm.com/investor/news/jun-2005/03-06-05-2.phtml

 

[keith]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On Fri, 17 Jun 2005 05:02:57 +0000, Robert Redelmeier wrote:

> In comp.sys.ibm.pc.hardware.chips keith <krw@att.bizzzz> wrote:
>> Discontinuities? PLease. The fact is that the local loop
>> has becoem far quieter than in years past
>
> New or rewired loops, yes. I'm not sure how old loops
> magically improve

Many old loops were already fairly quiet. Many have been replaced. The
ones that aren't quiet don't get a speed bump. Too bad. I had two line a
few years back. The original line wouldn't go over 26K, while the newer
one was reliably 53K.

> But there still are discontinuities at splices. Maybe not much with the
> newer ones, but every little bit hurts, especially at higher
> frequencies.

Any discontinuity at a splice is peanuts at these frequencies. That's
like the people replacing their internal house wiring with cat-5,
expecting to see better perfromance.
>
>> (and likely to get even more so as people ditch wires).
>
> I take that to mean bury. Yes. I worry a little the aerial messenger
> could form a notch filter much like that demo of uniform stapling coax
> ruining TV. Of course nothing that would affect voice freqs.

No, I meant get rid of their land-lines completely.

>> The gain isn't because of some new magic, but because the S/N ratio is
>> better than what was expected. ...not to mention that the "last mile"
>> isn't twenty miles these days.
>
> Agreed. RTs are installed more often, but many city dwellers are on
> shorter but older loops.

Most of those loops are already pretty quiet. A friend's house is one of
the original (built between 1800 and 1803) structures in the village.
The loop isn't quite that old though. ;-) He has no problem at 53K. Old
wire isn't noiser than new wire (assuming twisted pair, not the individual
wires on the tree).

--
Keith

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Fri, 17 Jun 2005 07:01:26 -0500, "Del Cecchi"
<dcecchi.nospam@att.net> wrote:

>
><rbmyersusa@gmail.com> wrote in message
>news:1118959746.898811.150630@f14g2000cwb.googlegroups.com...
>> Del Cecchi wrote:
>>
>>>
>>> And did you notice that some brilliant outfit came out with a
>>> statistical timing analysis program for timing chip designs?
>>>
>>
>> As you know, I try to keep track of everything under the sun, but I
>> missed this one. Can you suggest a link?
>>
>> RM
>>
>Why, certainly.
>
>http://www.ibm.com/investor/news/jun-2005/03-06-05-2.phtml
>

Thanks. One piece of news there, of course, is that IBM is offering
its own tools (and, I suspect, your services) to the public.

That news says something about the importance of process variability.
It doesn't say how fast the problem is getting worse, and
electromigration is a problem on top of that.

Most of the scaling predictions we've seen (Moore's law will break
down at some particular scale) have turned out to be wrong, but sooner
or later, this (process variability, leakage, electromigration) all
has to catch up with us. I suppose a great many people would like to
know when.

RM

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Robert Myers wrote:
> On Fri, 17 Jun 2005 07:01:26 -0500, "Del Cecchi"
> <dcecchi.nospam@att.net> wrote:
>
>
>><rbmyersusa@gmail.com> wrote in message
>>news:1118959746.898811.150630@f14g2000cwb.googlegroups.com...
>>
>>>Del Cecchi wrote:
>>>
>>>
>>>>And did you notice that some brilliant outfit came out with a
>>>>statistical timing analysis program for timing chip designs?
>>>>
>>>
>>>As you know, I try to keep track of everything under the sun, but I
>>>missed this one. Can you suggest a link?
>>>
>>>RM
>>>
>>
>>Why, certainly.
>>
>>http://www.ibm.com/investor/news/jun-2005/03-06-05-2.phtml
>>
>
>
> Thanks. One piece of news there, of course, is that IBM is offering
> its own tools (and, I suspect, your services) to the public.
>
> That news says something about the importance of process variability.
> It doesn't say how fast the problem is getting worse, and
> electromigration is a problem on top of that.
>
> Most of the scaling predictions we've seen (Moore's law will break
> down at some particular scale) have turned out to be wrong, but sooner
> or later, this (process variability, leakage, electromigration) all
> has to catch up with us. I suppose a great many people would like to
> know when.
>
> RM

IBM has been offering the services of a goodly number of expert
designers at all levels from silicon wafer to system to software "to the
public" (assuming said public has enough money) for a few years now as
E&TS.

My personal opinion is that the problems you mention will slow progress
in a gradual fashion, rather than acting like a wall. The improvement
between generations will gradually become less, and the time span greater.


--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips keith <krw@att.bizzzz> wrote:
> I had two line a few years back. The original line wouldn't
> go over 26K, while the newer one was reliably 53K.

Sounds like load coils on the old line.

> Any discontinuity at a splice is peanuts at these
> frequencies. That's like the people replacing their internal
> house wiring with cat-5, expecting to see better perfromance.

And they usually won't. But push the distance and you also
get more splices. It doesn't help at 1.1 MHz.

> No, I meant get rid of their land-lines completely.

Fine for short ranges or low bandwidth.

> structures in the village. The loop isn't quite that old
> though. ;-) He has no problem at 53K. Old wire isn't noiser
> than new wire (assuming twisted pair, not the individual
> wires on the tree).

My parents house is also much older, with older wiring they
only get 48k . That's still no load coils, but the line is
starting to limit. At 8kft, they probably could get DSL 1.5 .

-- Robert

 

[keith]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On Fri, 17 Jun 2005 13:32:35 +0000, Robert Redelmeier wrote:

> In comp.sys.ibm.pc.hardware.chips keith <krw@att.bizzzz> wrote:
>> I had two line a few years back. The original line wouldn't
>> go over 26K, while the newer one was reliably 53K.
>
> Sounds like load coils on the old line.

Nope, it went all the way back to the CO, rather than a "slick" in the
neighborhood.

>> Any discontinuity at a splice is peanuts at these
>> frequencies. That's like the people replacing their internal
>> house wiring with cat-5, expecting to see better perfromance.
>
> And they usually won't. But push the distance and you also
> get more splices. It doesn't help at 1.1 MHz.

Oh, we're talking about different things. I thougth we were talking POTS.
If you take the POTS DACS out of the line you can up the frequency, which
is the other data-rate knob to twist. POTS is stuck with the 8kHz DAC, so
the only available knob is S/N.

>> No, I meant get rid of their land-lines completely.
>
> Fine for short ranges or low bandwidth.

Let me back up... As people ditch their phone lines, the rest become
quieter. ;-)/2

>> structures in the village. The loop isn't quite that old though. ;-)
>> He has no problem at 53K. Old wire isn't noiser than new wire
>> (assuming twisted pair, not the individual wires on the tree).
>
> My parents house is also much older, with older wiring they only get 48k
> . That's still no load coils, but the line is starting to limit. At
> 8kft, they probably could get DSL 1.5 .

Again, I thought we were talking about V.9x sorts of things.

--
Keith

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

In comp.sys.ibm.pc.hardware.chips keith <krw@att.bizzzz> wrote:
> Nope, it went all the way back to the CO, rather than a
> "slick" in the neighborhood.

Yes, but if it's a long or boraderline run, it could get
load coils.

> Oh, we're talking about different things. I thougth we were
> talking POTS. If you take the POTS DACS out of the line you can
> up the frequency, which is the other data-rate knob to twist.

Yes. I was thinking specifically of DSL. For POTS, that
prof's estimate of 20k being max isn't really all that far
of 53k. Only a factor of 2.6

> Let me back up... As people ditch their phone lines,
> the rest become quieter. ;-)/2

Of course. Particularly if they aren't carrying modem
signals for hours on end.

-- Robert