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Integrated memory controllers for Xeons & Itaniums

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Anonymous
a b à CPUs
a b } Memory
June 16, 2005 10:37:17 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

Intel to add memory controllers to future Xeons, Itanics | The Register
http://www.theregister.co.uk/2005/06/16/intel_integrate...
Anonymous
a b à CPUs
a b } Memory
June 17, 2005 10:23:09 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel (More info?)

On 16 Jun 2005 06:37:17 -0700, "YKhan" <yjkhan@gmail.com> wrote:

>Intel to add memory controllers to future Xeons, Itanics | The Register
>http://www.theregister.co.uk/2005/06/16/intel_integrate...

Hmm, as speculated here: cph1r0pq89669dd4di76ap40gj0phckjui@4ax.com last
December. The really interesting part of this is what they use for a
CPU/system interconnect... IOW the equivalent of Hypertransport.

--
Rgds, George Macdonald
!