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Gaming AMD vs Intel

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Anonymous
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September 4, 2005 12:15:25 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

I read the following article

http://tinyurl.com/8s2aa
on amdzone.com.



Extremetech looks at gameplay experience comparing AMD and Intel CPUs.
I'm surprised they used DDR2 533, but then of course if they were on
the real ball they would be using faster than DDR400 using the Lanparty
board with that 3500+.
The results speak for themselves. The average frame rate across all six
games for the Athlon 64 system is 61fps, while the Pentium 4 averaged
54fps. That's a 13% difference-not tiny, but not large enough to bowl
us over. What is more important, we feel, is how often a game runs
slowly enough that you can feel it. This methodology is consistent with
the one used by a new performance analysis tool in the works at Intel.
We picked arbitrary performance thresholds, but these are numbers based
on years of game playing experience. We picked frame rates at which you
actually notice an impact on how the game feels, not the absolute
minimum required to play and enjoy a game. This is where the Athlon 64
really kicks the Pentium 4 in the teeth. Our P4 system spent almost a
third of the time, across all games, beneath our target minimum FPS.
The Athlon 64 system, on the other hand, spent only 14% of its time
there. This is a difference of a whopping 121%!



"


So I am wanting to get a new system later this fall. I have read other
reviews saying Intel is the way to go for gaming.

I am looking for the best performance in games and for burning dvds/cds
and web browsing. But the high intensity graphics will be from games
like Doom 3.

I don't want a system that will choke on the graphics. I was thiking
about the nvidia latest pci-e card.

Any thoughts on intel vs AMD?

More about : gaming amd intel

Anonymous
a b à CPUs
September 4, 2005 9:06:25 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...
>I read the following article
>
> http://tinyurl.com/8s2aa
> on amdzone.com.

[quote from link snipped]

> So I am wanting to get a new system later this fall. I have read other
> reviews saying Intel is the way to go for gaming.

What reviews?

> I am looking for the best performance in games and for burning dvds/cds
> and web browsing. But the high intensity graphics will be from games
> like Doom 3.
>
> I don't want a system that will choke on the graphics. I was thiking
> about the nvidia latest pci-e card.
>
> Any thoughts on intel vs AMD?
>

Yes, AMD all the way.
--
Derek
Anonymous
a b à CPUs
September 4, 2005 10:36:13 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...
>I read the following article
>
> http://tinyurl.com/8s2aa
> on amdzone.com.
>
>
>
> Extremetech looks at gameplay experience comparing AMD and Intel CPUs.
> I'm surprised they used DDR2 533, but then of course if they were on
> the real ball they would be using faster than DDR400 using the Lanparty
> board with that 3500+.
> The results speak for themselves. The average frame rate across all six
> games for the Athlon 64 system is 61fps, while the Pentium 4 averaged
> 54fps. That's a 13% difference-not tiny, but not large enough to bowl
> us over. What is more important, we feel, is how often a game runs
> slowly enough that you can feel it. This methodology is consistent with
> the one used by a new performance analysis tool in the works at Intel.
> We picked arbitrary performance thresholds, but these are numbers based
> on years of game playing experience. We picked frame rates at which you
> actually notice an impact on how the game feels, not the absolute
> minimum required to play and enjoy a game. This is where the Athlon 64
> really kicks the Pentium 4 in the teeth. Our P4 system spent almost a
> third of the time, across all games, beneath our target minimum FPS.
> The Athlon 64 system, on the other hand, spent only 14% of its time
> there. This is a difference of a whopping 121%!
>
>
>
> "
>
>
> So I am wanting to get a new system later this fall. I have read other
> reviews saying Intel is the way to go for gaming.
>
> I am looking for the best performance in games and for burning dvds/cds
> and web browsing. But the high intensity graphics will be from games
> like Doom 3.
>
> I don't want a system that will choke on the graphics. I was thiking
> about the nvidia latest pci-e card.
>
> Any thoughts on intel vs AMD?
>

Yep, just tell the devs and hardware makers to come up with some 64 bit code
now :) 
McG.
Related resources
Anonymous
a b à CPUs
September 5, 2005 2:35:41 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

You would be happy with AMD or Intel, both would play games just fine.
I personal would go AMD as the price for performance is cheaper with AMD.
AMD also beat Intel to coming out with 64 bit CPUs

Rumors are that the new ATI coming out soon is faster then NVIDIA

<Conservative.Nate@gmail.com> wrote in message
news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...
>I read the following article
>
> http://tinyurl.com/8s2aa
> on amdzone.com.
>
>
>
> Extremetech looks at gameplay experience comparing AMD and Intel CPUs.
> I'm surprised they used DDR2 533, but then of course if they were on
> the real ball they would be using faster than DDR400 using the Lanparty
> board with that 3500+.
> The results speak for themselves. The average frame rate across all six
> games for the Athlon 64 system is 61fps, while the Pentium 4 averaged
> 54fps. That's a 13% difference-not tiny, but not large enough to bowl
> us over. What is more important, we feel, is how often a game runs
> slowly enough that you can feel it. This methodology is consistent with
> the one used by a new performance analysis tool in the works at Intel.
> We picked arbitrary performance thresholds, but these are numbers based
> on years of game playing experience. We picked frame rates at which you
> actually notice an impact on how the game feels, not the absolute
> minimum required to play and enjoy a game. This is where the Athlon 64
> really kicks the Pentium 4 in the teeth. Our P4 system spent almost a
> third of the time, across all games, beneath our target minimum FPS.
> The Athlon 64 system, on the other hand, spent only 14% of its time
> there. This is a difference of a whopping 121%!
>
>
>
> "
>
>
> So I am wanting to get a new system later this fall. I have read other
> reviews saying Intel is the way to go for gaming.
>
> I am looking for the best performance in games and for burning dvds/cds
> and web browsing. But the high intensity graphics will be from games
> like Doom 3.
>
> I don't want a system that will choke on the graphics. I was thiking
> about the nvidia latest pci-e card.
>
> Any thoughts on intel vs AMD?
>
Anonymous
a b à CPUs
September 5, 2005 4:48:10 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On 4 Sep 2005 08:15:25 -0700, Conservative.Nate@gmail.com wrote:

>I read the following article
>
>http://tinyurl.com/8s2aa
>on amdzone.com.

Hehe, www.amdzone.com is, not surprisingly, a VERY pro-AMD/anti-Intel
site, so don't expect to see anything except "AMD is the greatest"
from them! That being said, the article they are quoting is from a
much less biased source.

>So I am wanting to get a new system later this fall. I have read other
>reviews saying Intel is the way to go for gaming.

??? Really? When it comes to gaming Intel has been beaten pretty
soundly in virtually all tests I've seen since the Athlon64 was
released two years ago. Gaming is one area where AMD has the most
definite and obvious performance lead.

>I am looking for the best performance in games and for burning dvds/cds
>and web browsing. But the high intensity graphics will be from games
>like Doom 3.

AMD's Athlon64 chips are unquestionably the way to go for gaming
performance IMO. Their performance/dollar is a fair bit higher than
Intel's pretty much across the board, from their low-end (Socket 754)
Sempron models right up to their top-end Athlon64 FX chips. Dollar
for dollar the AMD chips are usually ~15-20% faster.

>I don't want a system that will choke on the graphics. I was thiking
>about the nvidia latest pci-e card.

If you can afford it, the nVidia GeForce 7800 GTX is the best out
there. Alternatively there is the 7800GT which offers close to the
same performance with a price tag that's about $100 less.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 5, 2005 4:53:51 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

AMD is more than just cheaper,they are significantly faster in gameplay,run
much cooler,and were the first with dual core,which could take away the one
edge Intel had in multi-tasking.
As for ATI,they better get a move on if they want to keep pace with
Nvidia,so far all I've heard from them is rumors.They've been promising
Crossfire for months,while Nvidia's SLI has already been here for months,and
the 7800 series gets faster with each new version released.
"tod" <no_spam_i@earthlink.net> wrote in message
news:1FKSe.5326$4P5.4248@newsread2.news.pas.earthlink.net...
> You would be happy with AMD or Intel, both would play games just fine.
> I personal would go AMD as the price for performance is cheaper with AMD.
> AMD also beat Intel to coming out with 64 bit CPUs
>
> Rumors are that the new ATI coming out soon is faster then NVIDIA
>
> <Conservative.Nate@gmail.com> wrote in message
> news:1125846925.400356.26180@z14g2000cwz.googlegroups.com...
> >I read the following article
> >
> > http://tinyurl.com/8s2aa
> > on amdzone.com.
> >
> >
> >
> > Extremetech looks at gameplay experience comparing AMD and Intel CPUs.
> > I'm surprised they used DDR2 533, but then of course if they were on
> > the real ball they would be using faster than DDR400 using the Lanparty
> > board with that 3500+.
> > The results speak for themselves. The average frame rate across all six
> > games for the Athlon 64 system is 61fps, while the Pentium 4 averaged
> > 54fps. That's a 13% difference-not tiny, but not large enough to bowl
> > us over. What is more important, we feel, is how often a game runs
> > slowly enough that you can feel it. This methodology is consistent with
> > the one used by a new performance analysis tool in the works at Intel.
> > We picked arbitrary performance thresholds, but these are numbers based
> > on years of game playing experience. We picked frame rates at which you
> > actually notice an impact on how the game feels, not the absolute
> > minimum required to play and enjoy a game. This is where the Athlon 64
> > really kicks the Pentium 4 in the teeth. Our P4 system spent almost a
> > third of the time, across all games, beneath our target minimum FPS.
> > The Athlon 64 system, on the other hand, spent only 14% of its time
> > there. This is a difference of a whopping 121%!
> >
> >
> >
> > "
> >
> >
> > So I am wanting to get a new system later this fall. I have read other
> > reviews saying Intel is the way to go for gaming.
> >
> > I am looking for the best performance in games and for burning dvds/cds
> > and web browsing. But the high intensity graphics will be from games
> > like Doom 3.
> >
> > I don't want a system that will choke on the graphics. I was thiking
> > about the nvidia latest pci-e card.
> >
> > Any thoughts on intel vs AMD?
> >
>
>
Anonymous
a b à CPUs
September 5, 2005 6:59:40 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

I agree that a label is not what makes gaming interesting. I too have used
them all. Although I must admit this is the first time I broke my AMD
cherry a few weeks ago and so far am very satisfied/ FX 57. I also just
got two 7800 SLI and that's great too. Before that though it was a coup of
years or so of ATI which before that was an even longer period of Nvdia in
the ATI maybe bad driver support days.
The one thing you never hear about is a Creative fan boy because the
have been the masters of the monopoly game. They just quietly go about
doing nothing all that radical as far as I am concerned. There is not a
doubt in my mind that if creative had it's equivalent competitor like in the
graphics and cpu arena sound would be better also. Not that there is
anything greatly wrong with creative sound ,particularly when most people
play their games through low end speakers nowhere comparable to our high end
or even middle end home or these days even car speakers.
I play my games through my reasonably high end home stereo 5.1
surround system. The sub woofer is 800 watts and it actually hurts to get
hit by artillery in Battlefront 2 as I sit right next to it. Never the less
to say I can really tell the difference between my various creative live and
audigy cards is not really being too forward. they all sound fine to me but
not like my DVDs and music disks. I have been gaming since pong in the
seventies. I don't ever remember once pc gaming took effect a time when
anybody but Creative had any kind of a foot hold. I do remember cursing
them in the old DOS days when like 80% of computer problems were sound card
related.

"Tony Hill" <hilla_nospam_20@yahoo.ca> wrote in message
news:92jnh1ho20erfg6jp0935ae3cctc4sv2e2@4ax.com...
> On 4 Sep 2005 08:15:25 -0700, Conservative.Nate@gmail.com wrote:
>
>>I read the following article
>>
>>http://tinyurl.com/8s2aa
>>on amdzone.com.
>
> Hehe, www.amdzone.com is, not surprisingly, a VERY pro-AMD/anti-Intel
> site, so don't expect to see anything except "AMD is the greatest"
> from them! That being said, the article they are quoting is from a
> much less biased source.
>
>>So I am wanting to get a new system later this fall. I have read other
>>reviews saying Intel is the way to go for gaming.
>
> ??? Really? When it comes to gaming Intel has been beaten pretty
> soundly in virtually all tests I've seen since the Athlon64 was
> released two years ago. Gaming is one area where AMD has the most
> definite and obvious performance lead.
>
>>I am looking for the best performance in games and for burning dvds/cds
>>and web browsing. But the high intensity graphics will be from games
>>like Doom 3.
>
> AMD's Athlon64 chips are unquestionably the way to go for gaming
> performance IMO. Their performance/dollar is a fair bit higher than
> Intel's pretty much across the board, from their low-end (Socket 754)
> Sempron models right up to their top-end Athlon64 FX chips. Dollar
> for dollar the AMD chips are usually ~15-20% faster.
>
>>I don't want a system that will choke on the graphics. I was thiking
>>about the nvidia latest pci-e card.
>
> If you can afford it, the nVidia GeForce 7800 GTX is the best out
> there. Alternatively there is the 7800GT which offers close to the
> same performance with a price tag that's about $100 less.
>
> -------------
> Tony Hill
> hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 5, 2005 8:22:51 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Conservative.Nate@gmail.com wrote:
> So I am wanting to get a new system later this fall. I have read other
> reviews saying Intel is the way to go for gaming.

Those reviews must be several years old now. AMD has been tightening
its hold on the gaming market steady for the past 2-3 years now,
basically since the Athlon 64 first came out. Prior to that there was a
period of time (about 6 years ago to 4 years ago) when Intel and AMD
were trading top spot almost on a weekly basis. Then for a period of
one year, from about 4 years ago to about 3 years ago, Intel had the
crown for itself for about a year, as AMD dropped out to concentrate on
getting the Athlon 64 out.

Now, it's possible that AMD and Intel will switch positions once again
in this field, like they have in the past. But there's some evidence
that AMD will have this crown for several more years still. In the
transition from the Athlon XP to the Athlon 64, AMD took the time to
not only improve the design of chips, but it actually redesign some
very basic concepts of its chips. One example is that the ubiquitous
front-side bus (FSB), namely AMD got rid of it! The FSB was the method
by which PC chips had connected to their peripheral devices and its
memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
replaced it with two seperate connections, one for the memory and one
for the peripherals. Intel isn't expected to have a similar system till
at least 2007; and it's not likely that AMD will remain stagnant
waiting for Intel to catch up during that time.

> I am looking for the best performance in games and for burning dvds/cds
> and web browsing. But the high intensity graphics will be from games
> like Doom 3.

None of those tasks are all that demanding for today's generation of
processors.

> I don't want a system that will choke on the graphics. I was thiking
> about the nvidia latest pci-e card.
>
> Any thoughts on intel vs AMD?

Well, you touched on one thing that is very important these days: the
graphics card. The performance war at the CPU level has sort of taken a
backseat to the war of the video cards for gaming. It's not so much
Intel vs. AMD as it is Nvidia vs. ATI.

That being said, AMD does offer some interesting advantages to aid your
choice of video cards. These days video cards have gotten into a
dual-core battle of their own, ATI offers its Crossfire technology,
while Nvidia offers its SLI technology. Due to the seperated memory and
peripheral connection paths that AMD offers in Athlon 64 these days,
both Crossfire and SLI work much better under an AMD processor than in
an Intel processor. I think the numbers they have come up with
generally show that a Crossfire or SLI system will show a 40%
improvement under Intel, but an 80% improvement under AMD.

And that's not all, although this is something that's for the future,
and won't affect any processor purchase that you make today, there was
a rumour that AMD has decided to integrate a PCI-e interface directly
into the processor, which would offer even higher performance for SLI
or Crossfire. But that's something probably two years out too.

Yousuf Khan
Anonymous
a b à CPUs
September 6, 2005 10:14:02 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:

> not only improve the design of chips, but it actually redesign some
> very basic concepts of its chips. One example is that the ubiquitous
> front-side bus (FSB), namely AMD got rid of it! The FSB was the method
> by which PC chips had connected to their peripheral devices and its
> memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
> replaced it with two seperate connections, one for the memory and one
> for the peripherals.

For clearity, AMD didn't get rid of the FSB, they just stopped calling it
a FSB, even though that's what it still is, by definition. They did
however move the memory controller onto the cpu, so that ram data now has
it's own data path to the CPU. This move, and not the move to an HT link
for the FSB is where the major performance gain was made. With the move to
the seperate memory bus, the FSB (now a serial HT link, instead of a
paralell bus) speed is of little importance.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm
Anonymous
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September 6, 2005 10:14:03 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Tue, 06 Sep 2005 06:14:02 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:

>On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:
>
>> not only improve the design of chips, but it actually redesign some
>> very basic concepts of its chips. One example is that the ubiquitous
>> front-side bus (FSB), namely AMD got rid of it! The FSB was the method
>> by which PC chips had connected to their peripheral devices and its
>> memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
>> replaced it with two seperate connections, one for the memory and one
>> for the peripherals.
>
>For clearity, AMD didn't get rid of the FSB, they just stopped calling it
>a FSB, even though that's what it still is, by definition.

The term FSB came about with Intel's Pentium Pro, where the dual chip
CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
<-> L2 cache data as well as I/O and memory transfers. By definition, a
FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
cache transfers. To me calling AMD's HT a FSB is about as valid as
continuing to use North Bridge & South Bridge for the two chips normally
used in a chipset - it's not really applicable any more but people will say
it as a convenience term

> They did
>however move the memory controller onto the cpu, so that ram data now has
>it's own data path to the CPU. This move, and not the move to an HT link
>for the FSB is where the major performance gain was made. With the move to
>the seperate memory bus, the FSB (now a serial HT link, instead of a
>paralell bus) speed is of little importance.

As recently discussed here, HyperTransport is not a serial bus - it *is*
packetized and it is point-to-point/uni-directional but each byte-width
path has a separate clock signal and the chip/system designers have to pay
close attention to clock skew.

As far as speed, with current Athlon64 systems, the 2-byte-wide down-link
from CPU->chipset->PCI-e(x16) is, in theory, maxed out at the 1GHz clock
rate. Put another way, the current PCI-e x16 graphics path has a max
bandwidth of 4.1GB/s; the HT down-link has a max bandwidth of 4GB/s so in
theory, at least, it would be possible for memory->graphics transfers to
saturate the HT down-link.

I don't think this is a problem for the moment but add in that the 4GB/s HT
up-link for an integrated graphics chipset could be seriously stressed and
cause HT traffic contention, it could lead to problems down the road... as
well as supply ammo to anti-AMD marketing efforts. So yes, speed of HT is
an issue and the integrated PCI-e that AMD is adding will help mitigate
those err, concerns.

--
Rgds, George Macdonald
Anonymous
a b à CPUs
September 6, 2005 12:52:06 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

>Or, if your pockets allow for it, go for dual
>dual-core Opteron, making it a quad. Maybe today's games can't take
>real advantage of multithreading, but I bet the games of tomorrow (and
>not only games) are already being coded to use multiple cores to their
>advantage.

Forgive me, I have not read much about Opteron chips. Are you saying
a system with dual 64 bit Opteron chips is about the same as what a
QUAD A64 X2 would be ?
Anonymous
a b à CPUs
September 6, 2005 1:53:48 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Conservative.N...@gmail.com wrote:
> >Or, if your pockets allow for it, go for dual
> >dual-core Opteron, making it a quad. Maybe today's games can't take
> >real advantage of multithreading, but I bet the games of tomorrow (and
> >not only games) are already being coded to use multiple cores to their
> >advantage.
>
> Forgive me, I have not read much about Opteron chips. Are you saying
> a system with dual 64 bit Opteron chips is about the same as what a
> QUAD A64 X2 would be ?

No, A64 systems are limited to one and only one CPU socket. So if you
have a dual-core A64, then that's all you're ever going to get: two
cores. However, Opteron workstations often have dual sockets, and
dual-core Opterons in each socket will mean that you have upto four
cores.

Yousuf Khan
Anonymous
a b à CPUs
September 6, 2005 2:08:36 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

To me, a bus would be a multi-drop access medium, with multiple devices
(including CPUs) all sharing a single data path between each other.
Hypertransport is a point-to-point interface, you can only connect to
one other device with each HT link. This would be much the same as old
collision-based Ethernet vs. switched Ethernet.

Yousuf Khan
Anonymous
a b à CPUs
September 6, 2005 11:13:54 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:

>>For clearity, AMD didn't get rid of the FSB, they just stopped calling it
>>a FSB, even though that's what it still is, by definition.
>
> The term FSB came about with Intel's Pentium Pro, where the dual chip
> CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
> CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
> <-> L2 cache data as well as I/O and memory transfers. By definition, a
> FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
> cache transfers. To me calling AMD's HT a FSB is about as valid as
> continuing to use North Bridge & South Bridge for the two chips normally
> used in a chipset - it's not really applicable any more but people will say
> it as a convenience term
>
FSB by definition connects the CPU to the chipset. HT link by definition
is just that, any bus using HT technolog and is not limited to
connections between a cpu and a chipset. So given the choice of
calling the bus a FSB, or the HT link, FSB fits the bill while HT link
only describes the type of bus, not the bus itself. IOW's using the term
FSB specifically refers to the connection between the CPU and chipset,
while using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus, but
that's generic in nature and could even refer to the memory bus since it's
a part of the system. So, imo, the bus conncetion between the cpu and
chipset is still a FSB, thus specifically stating what the two ends
actually connect to. Simply calling it an HT link doesn't descibe any
particular bus, and shouldn't be assumed that it means a conncetion
between a xpu and its chipset, as HT links are currently being used for
other purposes. Be it convenient or not, it's still there.

>> They did
>>however move the memory controller onto the cpu, so that ram data now has
>>it's own data path to the CPU. This move, and not the move to an HT link
>>for the FSB is where the major performance gain was made. With the move to
>>the seperate memory bus, the FSB (now a serial HT link, instead of a
>>paralell bus) speed is of little importance.
>
> As recently discussed here, HyperTransport is not a serial bus - it *is*
> packetized and it is point-to-point/uni-directional but each byte-width
> path has a separate clock signal and the chip/system designers have to pay
> close attention to clock skew.
>
I'll go with you on this. Probably a paralell packet network would
describe it better.

--
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September 7, 2005 2:18:40 AM

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On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

> On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:
>
>>>For clearity, AMD didn't get rid of the FSB, they just stopped calling it
>>>a FSB, even though that's what it still is, by definition.
>>
>> The term FSB came about with Intel's Pentium Pro, where the dual chip
>> CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
>> CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
>> <-> L2 cache data as well as I/O and memory transfers. By definition, a
>> FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
>> cache transfers. To me calling AMD's HT a FSB is about as valid as
>> continuing to use North Bridge & South Bridge for the two chips normally
>> used in a chipset - it's not really applicable any more but people will say
>> it as a convenience term
>>
> FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side <cache> bus"
of the P6. The P5 had no "FSB".

> HT link by definition
> is just that, any bus using HT technolog and is not limited to
> connections between a cpu and a chipset.

Only in your mind. It is in no way an "FSB", since the term is now
meaningless. The memory bus is elsewhere, so if there *IS* an "FSB" it's
the memory bus(ses), not the HT channel. The caches are on the
"back-side" of the memory interface, not other procesors or I/O.

> So given the choice of calling
> the bus a FSB, or the HT link, FSB fits the bill while HT link only
> describes the type of bus, not the bus itself.

FSB doesn't describe it's function at all. What's the "back side" of the
HT link?

> IOW's using the term FSB
> specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are on
the other side (back side) of the P6 memory bus. That architecture was
around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there, since it
no longer describes any function.


> while
> using the term HT link could be any of many different type of
> connections an HT link is used for since it's used in many more
> applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.

> but
> that's generic in nature and could even refer to the memory bus since
> it's a part of the system.

Since it is the intervace from the processor to the "system", it still
makes sense. "FSB" makes *no* sense, since it's not on the "front" side
of anything.

> So, imo, the bus conncetion between the cpu
> and chipset is still a FSB, thus specifically stating what the two ends
> actually connect to. Simply calling it an HT link doesn't descibe any
> particular bus, and shouldn't be assumed that it means a conncetion
> between a xpu and its chipset, as HT links are currently being used for
> other purposes. Be it convenient or not, it's still there.

Your opinion and $2 may be useful in a Starbuck's. They don't much care
if you're wrong, as long as you have $2.

>>> They did
>>>however move the memory controller onto the cpu, so that ram data now
>>>has it's own data path to the CPU. This move, and not the move to an HT
>>>link for the FSB is where the major performance gain was made. With the
>>>move to the seperate memory bus, the FSB (now a serial HT link, instead
>>>of a paralell bus) speed is of little importance.
>>
>> As recently discussed here, HyperTransport is not a serial bus - it
>> *is* packetized and it is point-to-point/uni-directional but each
>> byte-width path has a separate clock signal and the chip/system
>> designers have to pay close attention to clock skew.
>>
> I'll go with you on this. Probably a paralell packet network would
> describe it better.

Whatever, but it is *NOT* an "FSB". AMD has broken out of that system
architecture. ...much like Intel broke into it by moving the L2 traffic
to the *BACK-SIDE* bus.

--
Keith
Anonymous
a b à CPUs
September 7, 2005 3:12:52 AM

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keith wrote:
> Nope. As George stated, it was in opposition the "back-side <cache> bus"
> of the P6. The P5 had no "FSB".

Maybe in those days it was better known as the "local bus".

Yousuf Khan
Anonymous
a b à CPUs
September 7, 2005 9:59:41 AM

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On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>
>> FSB by definition connects the CPU to the chipset.
>
> Nope. As George stated, it was in opposition the "back-side <cache> bus"
> of the P6. The P5 had no "FSB".
>
Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

While the term may have originated the way you say, it was then later used
to indicate the connection between the CPU and the chipset. Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory data
now has own single use bus for the memory. The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.

>> HT link by definition is just that, any bus using HT technolog and
>> is not limited to connections between a cpu and a chipset.
>
> Only in your mind. It is in no way an "FSB", since the term is now
> meaningless. The memory bus is elsewhere, so if there *IS* an "FSB"
> it's the memory bus(ses), not the HT channel. The caches are on the
> "back-side" of the memory interface, not other procesors or I/O.
>
And I thought only the government could take something so simple and
fiubar.

>> So given the choice of calling
>> the bus a FSB, or the HT link, FSB fits the bill while HT link only
>> describes the type of bus, not the bus itself.
>
> FSB doesn't describe it's function at all. What's the "back side" of
> the HT link?
>
What HT link? Ht links are used everywhere. AFAIK, they don't need a
backside. They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the chipset,
I'd just answer that it's in the same place as back side of the K7 CPU's
FSB. You're really digging a hole for yourself here.

>> IOW's using the term FSB
>> specifically refers to the connection between the CPU and chipset,
>
> No, it doesn't. I specifically refers to the fact that the caches are on
> the other side (back side) of the P6 memory bus. That architecture was
> around for a while, so it stuck. There was no "FSB" in the P5
> architecture. It's an invention of the P6 and should stay there, since
> it no longer describes any function.
>
Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset.
>
>> while
>> using the term HT link could be any of many different type of
>> connections an HT link is used for since it's used in many more
>> applications than just a FSB. Some refer to the bus as a system bus,
>
> "System bus" works for me. I/O bus makes more sense.
>
Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
buses. So how are you going to distinquish which one you are talking about
if you just use system bus? Damn, I wonder if FSB would do that?:-)
I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
an I/O bus.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
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Anonymous
a b à CPUs
September 7, 2005 1:14:00 PM

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On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:

>On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>
>> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>>
>>> FSB by definition connects the CPU to the chipset.
>>
>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
>> of the P6. The P5 had no "FSB".
>>
>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
>see just how many people you can convince of that.:-)

No, the K7s had (the equivalent of) a FSB though I'm not sure AMD ever
called it that IIRC.

>While the term may have originated the way you say, it was then later used
>to indicate the connection between the CPU and the chipset. Now, that same
>connection is the HT link of the K8. So it only makes sense to use the
>same terminology for the very specific connection even though memory data
>now has own single use bus for the memory. The FSB still carries all other
>IO operations to/from the system. Once they move all this into the CPU,
>there will no longer be a FSB. Until then, a duck by any other name is
>still a duck.

NO - the HT is more akin to the Intel Hub interface or the VIA-Link
interconnect between memory controller/AGP chip and the I/O chip; it was
AMD's attempt to establish a standard for that type of traffic... since
Intel had locked theirs up with licensing fees. Much of the old PC North
Bridge arbitration logic is now in the K8 CPU - it has to be to route to
the various memory address spaces and for DMA transfers.

>>> So given the choice of calling
>>> the bus a FSB, or the HT link, FSB fits the bill while HT link only
>>> describes the type of bus, not the bus itself.
>>
>> FSB doesn't describe it's function at all. What's the "back side" of
>> the HT link?
>>
>What HT link? Ht links are used everywhere. AFAIK, they don't need a
>backside. They function fully indepentant of other buses. If I assume you
>are talking about the HT link used to connect the K8 cpu's to the chipset,
>I'd just answer that it's in the same place as back side of the K7 CPU's
>FSB. You're really digging a hole for yourself here.

The equivalent of FSB on a K8 CPU is inside the CPU die - anything that
gets out to HT is already defined as I/O traffic. In no way is it a FSB.

--
Rgds, George Macdonald
Anonymous
a b à CPUs
September 7, 2005 8:48:31 PM

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"Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
news:p an.2005.09.07.06.03.43.197405@TAKEOUTverizon.net...
> On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>
> > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
> >
> >> FSB by definition connects the CPU to the chipset.
> >
> > Nope. As George stated, it was in opposition the "back-side
<cache> bus"
> > of the P6. The P5 had no "FSB".
> >
> Under your definition of FSB, then no AMD CPU's have ever had a FSB.
Let's
> see just how many people you can convince of that.:-)

Wes, are you saying no AMD chip ever had an L2 cache hung off the back
of the CPU? Wow, is _my_ memory ever going south! ;-)
Anonymous
a b à CPUs
September 7, 2005 10:57:23 PM

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On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:

> "Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
> news:p an.2005.09.07.06.03.43.197405@TAKEOUTverizon.net...
>> On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>>
>> > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>> >
>> >> FSB by definition connects the CPU to the chipset.
>> >
>> > Nope. As George stated, it was in opposition the "back-side
> <cache> bus"
>> > of the P6. The P5 had no "FSB".
>> >
>> Under your definition of FSB, then no AMD CPU's have ever had a FSB.
> Let's
>> see just how many people you can convince of that.:-)
>
> Wes, are you saying no AMD chip ever had an L2 cache hung off the back
> of the CPU? Wow, is _my_ memory ever going south! ;-)

Well, that's was what I said, but I wasn't thinking back past the K7 and
K8's, and I actually never paid much attention to what they called the
bus to the earlier cpu's that had cache on the MB. Was that an L2 cache? I
thought it was L1. Too long ago to remember and I'm too lazy to look it up.:-)
And I just remembered that the Slot A k7's had it's L2 cache on the cpu
board too, and not in the cpu die, but I don't recall AMD or anyone else
using back side bus for it.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
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September 7, 2005 10:57:24 PM

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On Wed, 07 Sep 2005 18:57:23 +0000, Wes Newell wrote:

> On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:
>
>> "Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
>> news:p an.2005.09.07.06.03.43.197405@TAKEOUTverizon.net...
>>> On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>>>
>>> > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>>> >
>>> >> FSB by definition connects the CPU to the chipset.
>>> >
>>> > Nope. As George stated, it was in opposition the "back-side
>> <cache> bus"
>>> > of the P6. The P5 had no "FSB".
>>> >
>>> Under your definition of FSB, then no AMD CPU's have ever had a FSB.
>> Let's
>>> see just how many people you can convince of that.:-)
>>
>> Wes, are you saying no AMD chip ever had an L2 cache hung off the back
>> of the CPU? Wow, is _my_ memory ever going south! ;-)
>
> Well, that's was what I said, but I wasn't thinking back past the K7 and
> K8's, and I actually never paid much attention to what they called the
> bus to the earlier cpu's that had cache on the MB.

K7s had the L2 on the "back side". It wasn't hooked into the external
bus, as was socket-7 (and before).

> Was that an L2 cache? I thought it was L1.

Modern processors have *long* had seperate I and D L1s, burried in the
instruction-fetch and load-store elements. The K7s L2 is certainly hung
off the "back-side", meaning not connected to the system bus. The K8
further seperates the I/O and memory busses, so there is no longer
soethign even resembling a "front-side bus". There is (are) memory
bus(ses) and HT link(s). Alghough, the HT link isn't just an I/O bus. It
also crries coherency information (but I/O must be cache coherent too).

> Too long ago to remember and
> I'm too lazy to look it up.:-) And I just remembered that the Slot A
> k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
> I don't recall AMD or anyone else using back side bus for it.

I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2. Even the K6-III has an on-chip L2, but allows an
on-board L3 (mine has a 2MB L3).

--
Keith
September 7, 2005 10:57:25 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:


>
>I'm from Missouri (close, but not really). I never remember a slot-A K7
>with on-board L2. Even the K6-III has an on-chip L2, but allows an
>on-board L3 (mine has a 2MB L3).

Slot-A didn't have on-die L2 cache.
K7-500 512K L2 (has a 650Mhz core)
http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg
September 8, 2005 1:32:38 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Wed, 07 Sep 2005 16:53:57 -0500, Ed wrote:

> On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:
>
>
>>
>>I'm from Missouri (close, but not really). I never remember a slot-A K7
>>with on-board L2. Even the K6-III has an on-chip L2, but allows an
>>on-board L3 (mine has a 2MB L3).
>
> Slot-A didn't have on-die L2 cache.

I didn't say it did. Note that the Slot-1 PII didn't have an integrated
cache either, but the cache was still on the "back side" of the chip. The
Slot-A K7 was no different.

> K7-500 512K L2 (has a 650Mhz core)
> http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg

Sheesh, learn *SOMETHING*! Do start with reading comprehension.

--
Keith
Anonymous
a b à CPUs
September 9, 2005 1:41:35 AM

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On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote:

>On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>
>> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>>
>>> FSB by definition connects the CPU to the chipset.
>>
>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
>> of the P6. The P5 had no "FSB".
>>
>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
>see just how many people you can convince of that.:-)

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have a
frontside bus (Intel had already gone to integrated cache by this
time).

Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
is only kinda-sorta a bus in itself. Really it's more of a
point-to-point link, though it's in that fuzzy area that blurs the
lines between the two a bit (where the GTL+ bus used in the P6 is
definitely a bus and Hypertransport is definitely not a bus, EV6 falls
somewhere in between).

>While the term may have originated the way you say, it was then later used
>to indicate the connection between the CPU and the chipset.

Yes, a lot of people incorrectly refer to the a connection between the
CPU and the chipset as a "Front Side Bus". Just because lots of
people make a mistake that doesn't mean that they are right.

People also still call the memory controller the "northbridge" and the
I/O chip a "southbridge", which also makes no sense given that they
are no longer being connected via PCI and they usually aren't bridges
at all. Again, just because people incorrectly use a term doesn't
make it correct.

> Now, that same
>connection is the HT link of the K8. So it only makes sense to use the
>same terminology for the very specific connection even though memory data
>now has own single use bus for the memory.

It doesn't make any sense with the AthlonXP or the P4 and it makes
MUCH less sense with the Athlon64/Opteron. Just because it's a common
mistake doesn't make it any less of a mistake.

> The FSB still carries all other
>IO operations to/from the system. Once they move all this into the CPU,
>there will no longer be a FSB. Until then, a duck by any other name is
>still a duck.

Yes, but that still doesn't make a goose a duck, even if lots of
people mix the two of them up.

>> FSB doesn't describe it's function at all. What's the "back side" of
>> the HT link?
>>
>What HT link? Ht links are used everywhere. AFAIK, they don't need a
>backside.

The point is that you can't have a "front side bus" unless you have a
corresponding "back side bus". Hypertransport does not have such a
corresponding back side so therefore it's not the "front side" of
anything.

Given that it's not the 'front side' of anything and, as others have
mentioned, it's not a 'bus' at all then it DEFINITELY is not a "Front
Side Bus".

> They function fully indepentant of other buses. If I assume you
>are talking about the HT link used to connect the K8 cpu's to the chipset,
>I'd just answer that it's in the same place as back side of the K7 CPU's
>FSB. You're really digging a hole for yourself here.

The original Athlon had a backside bus with to the cache chips on the
cartridge. This was later removed with the "Thunderbird" chips with
integrated cache. As such, from the "Thunderbird" on forward
(including all AthlonXP chips) there was no FSB on the AthlonXP. Same
goes for the PIII from the "Coppermine" onwards as well as ALL P4
chips. None of those have FSBs, despite the fact that many people
incorrectly use the term to describe the system bus of said chips.

>>> IOW's using the term FSB
>>> specifically refers to the connection between the CPU and chipset,
>>
>> No, it doesn't. I specifically refers to the fact that the caches are on
>> the other side (back side) of the P6 memory bus. That architecture was
>> around for a while, so it stuck. There was no "FSB" in the P5
>> architecture. It's an invention of the P6 and should stay there, since
>> it no longer describes any function.
>>
>Why are you stuck on the Pentium Pro. FSB has been used for years to
>indicate the connection between the CPU and the chipset.

The term "Front Side Bus" was never used with the Pentium chips
because there was only one bus. FSB came into computer use with the
PentiumPro where Intel introduced a chip with a Frontside Bus
(connecting to main memory and I/O) and a Backside bus (connecting to
cache). The terminology continued through the PII and early PIII
chips, as well as early Athlon chips, as they had two buses, one for
memory and I/O and the other for cache. For chips with only a single
bus the term "FSB" makes no sense. Never has and never will, no
matter how many people make such a mistake.

With the Athlon64 and Opteron it's just more obviously incorrect than
it is with the AthlonXP and P4 chips.

>>> while
>>> using the term HT link could be any of many different type of
>>> connections an HT link is used for since it's used in many more
>>> applications than just a FSB. Some refer to the bus as a system bus,
>>
>> "System bus" works for me. I/O bus makes more sense.
>>
>Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
>buses. So how are you going to distinquish which one you are talking about
>if you just use system bus? Damn, I wonder if FSB would do that?:-)
>I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
>an I/O bus.

Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
point-to-point link. PCI-E and AGP are also definitely not buses,
though I expect many people to incorrectly call them such. PCI and
ISA are buses

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 9, 2005 1:41:36 AM

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On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:
>> Too long ago to remember and
>> I'm too lazy to look it up.:-) And I just remembered that the Slot A
>> k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
>> I don't recall AMD or anyone else using back side bus for it.
>
>I'm from Missouri (close, but not really). I never remember a slot-A K7
>with on-board L2.

There were a *few* Slot-A K7 chips that had integrated L2, but they
were only released for compatibility purposes (much like what Intel
did with some of their later Slot-1 PIII chips, though AMD released
far fewer of such chips). You might even be able to find someone
still selling such a beast if you look hard enough, just do a search
for "Thunderbird Slot-A".

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 9, 2005 2:01:26 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Wes Newell wrote:
*
snip
>
> Serial technologies such as PCI Express and RapidIO require
> serial-deserializer interfaces and have the burden of extensive overhead
> in encoding parallel data into serial data, embedding clock information,
> re-acquiring and decoding the data stream. The parallel technology of
> HyperTransport needs no serdes and clock encoding overhead making it far
> more efficient in data transfers.
>
> I rest my case.;-)
>

The last paragraph you quote, shown above, is Clintonian at best, with
respect to comparing the physical aspects of HT and PCI-E.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
September 9, 2005 3:14:23 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Thu, 08 Sep 2005 21:41:36 -0400, Tony Hill wrote:

> On Wed, 07 Sep 2005 16:42:58 -0400, keith <krw@att.bizzzz> wrote:
>>> Too long ago to remember and
>>> I'm too lazy to look it up.:-) And I just remembered that the Slot A
>>> k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
>>> I don't recall AMD or anyone else using back side bus for it.
>>
>>I'm from Missouri (close, but not really). I never remember a slot-A K7
>>with on-board L2.
>
> There were a *few* Slot-A K7 chips that had integrated L2, but they
> were only released for compatibility purposes (much like what Intel
> did with some of their later Slot-1 PIII chips, though AMD released
> far fewer of such chips). You might even be able to find someone
> still selling such a beast if you look hard enough, just do a search
> for "Thunderbird Slot-A".

I meant the cache on the board (system bus), as opposed to "integrated"
or on the cartridge (on the "back-side").

--
Keith
September 9, 2005 3:29:38 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
> <w.newell@TAKEOUTverizon.net> wrote:
>
>>On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>>
>>> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>>>
>>>> FSB by definition connects the CPU to the chipset.
>>>
>>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
>>> of the P6. The P5 had no "FSB".
>>>
>>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
>>see just how many people you can convince of that.:-)
>
> Not true at all. The original AMD Athlon had both a front-side bus,
> connecting the CPU to the chipset, I/O and memory, and a backside bus
> that connected the CPU to the cache chips on the Slot-A cartridge.
> This was actually the last x86 CPU that I'm aware of which did have a
> frontside bus (Intel had already gone to integrated cache by this
> time).

Just because the cache is integrated doesn't mean the cache isn't on the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

> Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is
> only kinda-sorta a bus in itself. Really it's more of a point-to-point
> link, though it's in that fuzzy area that blurs the lines between the
> two a bit (where the GTL+ bus used in the P6 is definitely a bus and
> Hypertransport is definitely not a bus, EV6 falls somewhere in between).

Works for me.

>>While the term may have originated the way you say, it was then later
>>used to indicate the connection between the CPU and the chipset.
>
> Yes, a lot of people incorrectly refer to the a connection between the
> CPU and the chipset as a "Front Side Bus". Just because lots of people
> make a mistake that doesn't mean that they are right.

Yep! It ignores the reason it was called the "front-side bus" to begin
with.

> People also still call the memory controller the "northbridge" and the
> I/O chip a "southbridge", which also makes no sense given that they are
> no longer being connected via PCI and they usually aren't bridges at
> all. Again, just because people incorrectly use a term doesn't make it
> correct.

As long as there is an off-chip memory controller and high-speed
peripherals on the "bridge", it's proper to call it a "north-bridge". If
there is a low-spped bridge hanging off that, "south-bridge" is a useful
concept.

>> Now, that same
>>connection is the HT link of the K8. So it only makes sense to use the
>>same terminology for the very specific connection even though memory
>>data now has own single use bus for the memory.
>
> It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
> less sense with the Athlon64/Opteron. Just because it's a common
> mistake doesn't make it any less of a mistake.

Why doesn't "front-side bus" work with the P4 or K7? The cache is still
on the "back side" of the processor, even though it's on the chip.

<snip>

>> They function fully indepentant of other buses. If I assume you
>>are talking about the HT link used to connect the K8 cpu's to the
>>chipset, I'd just answer that it's in the same place as back side of the
>>K7 CPU's FSB. You're really digging a hole for yourself here.
>
> The original Athlon had a backside bus with to the cache chips on the
> cartridge. This was later removed with the "Thunderbird" chips with
> integrated cache. As such, from the "Thunderbird" on forward (including
> all AthlonXP chips) there was no FSB on the AthlonXP. Same goes for the
> PIII from the "Coppermine" onwards as well as ALL P4 chips. None of
> those have FSBs, despite the fact that many people incorrectly use the
> term to describe the system bus of said chips.

No, the back side bus wasn't removed. It was integrated onto the chip.
The architecture is the same, if the parts moved around.

>>>> IOW's using the term FSB
>>>> specifically refers to the connection between the CPU and chipset,
>>>
>>> No, it doesn't. I specifically refers to the fact that the caches are
>>> on the other side (back side) of the P6 memory bus. That architecture
>>> was around for a while, so it stuck. There was no "FSB" in the P5
>>> architecture. It's an invention of the P6 and should stay there,
>>> since it no longer describes any function.
>>>
>>Why are you stuck on the Pentium Pro. FSB has been used for years to
>>indicate the connection between the CPU and the chipset.
>
> The term "Front Side Bus" was never used with the Pentium chips because
> there was only one bus. FSB came into computer use with the PentiumPro
> where Intel introduced a chip with a Frontside Bus (connecting to main
> memory and I/O) and a Backside bus (connecting to cache). The
> terminology continued through the PII and early PIII chips, as well as
> early Athlon chips, as they had two buses, one for memory and I/O and
> the other for cache. For chips with only a single bus the term "FSB"
> makes no sense. Never has and never will, no matter how many people
> make such a mistake.

I dissagree. The back-side bus was integrated onto the chip. Again, the
memory architecture was the same.

> With the Athlon64 and Opteron it's just more obviously incorrect than it
> is with the AthlonXP and P4 chips.

It *is* incorrect, not so with the P4 or K7.

>>>> while
>>>> using the term HT link could be any of many different type of
>>>> connections an HT link is used for since it's used in many more
>>>> applications than just a FSB. Some refer to the bus as a system bus,
>>>
>>> "System bus" works for me. I/O bus makes more sense.
>>>
>>Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
>>buses. So how are you going to distinquish which one you are talking
>>about if you just use system bus? Damn, I wonder if FSB would do
>>that?:-) I/O bus. Ditto, and you can throw HTlink into the mix too since
>>it is also an I/O bus.

> Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
> point-to-point link. PCI-E and AGP are also definitely not buses,
> though I expect many people to incorrectly call them such. PCI and ISA
> are buses

True enough. Apparently some people call ducks geese too. ;-)

--
Keith
September 9, 2005 4:32:11 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

I believe this is a "setup" question. AMD has had superior processors
for quite some time now. Where have you been? AMD's superiority
began with the first Athlon processors, they had the first 64bit and
the first dual comsumer processor. It's dual kicks Intels butt big
time. Almost makes Intel look like they're in the dark ages they
are.

Assuming you already know the answer; what you may not know that most
AMD processors are unlocked and are quite easily over clocked and
Intel's are not. There is a reason, if Intels run any hotter, you
could heat your house with them.

Cooling, while not a glamorious subject, is the only thing giving you
a serious edge. Edge? Yeah, edge for tweaking, and edge for
longevity.

Gaming is not the only thing that gets a processor hot. I encode DVDs
from my old VCR tapes and writing chapters, pegs my processor for up
to 1/2 hour. That is much more an indicator of a faster processor,
then gaming is. Gaming stresses more then just the processor.

Using a TT Silent Boost cooler, my processor only gains about 4
degrees f. That's amazing.

Also, don't forget the video is just as important. Without good
video, all the processor power in the world won't help you for
gaming.
Anonymous
a b à CPUs
September 10, 2005 2:59:53 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:

>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>
>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>> <w.newell@TAKEOUTverizon.net> wrote:
>>
>> Not true at all. The original AMD Athlon had both a front-side bus,
>> connecting the CPU to the chipset, I/O and memory, and a backside bus
>> that connected the CPU to the cache chips on the Slot-A cartridge.
>> This was actually the last x86 CPU that I'm aware of which did have a
>> frontside bus (Intel had already gone to integrated cache by this
>> time).
>
>Just because the cache is integrated doesn't mean the cache isn't on the
>"back side" of the processor. The "back-side" concept was really a
>separation of the cache from the memory busses.

Ok, I'll grant that point. I would still say that it's not really an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 10, 2005 4:07:17 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

dannysdailys wrote:
> Assuming you already know the answer; what you may not know that most
> AMD processors are unlocked [...]

Not quite. Only the FX models are unlocked.

The other models allow lower multipliers for Cool and Quiet.
Anonymous
a b à CPUs
September 10, 2005 12:06:23 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Tony Hill wrote:

>
> It doesn't make any sense with the AthlonXP or the P4 and it makes
> MUCH less sense with the Athlon64/Opteron. Just because it's a common
> mistake doesn't make it any less of a mistake.
>

In matters of language, it does. Words lose their original meanings
and take on new meanings all the time. The notion of a bus as
something that can convey a signal is itself something of an
innovation, as a bus (or buss or busbar) was used in its original sense
to indicate something used to distribute power.

Using the term "front-side bus" to designate something other than what
the term referred to originally is an innovation, but it isn't wrong,
and it isn't even eccentric, because lots of people make the same
"mistake."

Only innovations in the ways that words are used aren't "mistakes,"
they are part of the natural process of by which language, and even
technical terminology, grows and evolves.

If there is confusion in a communication that results from a term being
used in a non-standard or ambiguous way, the confusion should be
addressed and the intended meaning clarified. Exploration of the
origins of a term and the different ways it has been used can be
enlightening and even fun.

Arguing over who is "right" and who is "wrong" just isn't any fun and
it enlightens no one.

RM
September 10, 2005 2:25:46 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:

> On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:
>
>>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>>
>>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>>> <w.newell@TAKEOUTverizon.net> wrote:
>>>
>>> Not true at all. The original AMD Athlon had both a front-side bus,
>>> connecting the CPU to the chipset, I/O and memory, and a backside bus
>>> that connected the CPU to the cache chips on the Slot-A cartridge.
>>> This was actually the last x86 CPU that I'm aware of which did have a
>>> frontside bus (Intel had already gone to integrated cache by this
>>> time).
>>
>>Just because the cache is integrated doesn't mean the cache isn't on the
>>"back side" of the processor. The "back-side" concept was really a
>>separation of the cache from the memory busses.
>
> Ok, I'll grant that point. I would still say that it's not really an
> accurate way of describing things when your 'bus' is connecting one
> half of a die to the other half of the die, but I suppose it is still
> a 'bus' of sorts, and certainly would be on the "backside" (relative
> to memory).

Why? There are *loads* of busses on processor chips, though most are
driven from a single end (bi-di gets messy). ...right down to the
power busses, though sometimes they're grids. ;-)

--
Keith
Anonymous
a b à CPUs
September 10, 2005 3:29:47 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

"keith" <krw@att.bizzzz> wrote in message
news:p an.2005.09.10.14.25.43.450875@att.bizzzz...
> On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:
>
>> On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:
>>
>>>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>>>
>>>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>>>> <w.newell@TAKEOUTverizon.net> wrote:
>>>>
>>>> Not true at all. The original AMD Athlon had both a front-side bus,
>>>> connecting the CPU to the chipset, I/O and memory, and a backside
>>>> bus
>>>> that connected the CPU to the cache chips on the Slot-A cartridge.
>>>> This was actually the last x86 CPU that I'm aware of which did have
>>>> a
>>>> frontside bus (Intel had already gone to integrated cache by this
>>>> time).
>>>
>>>Just because the cache is integrated doesn't mean the cache isn't on
>>>the
>>>"back side" of the processor. The "back-side" concept was really a
>>>separation of the cache from the memory busses.
>>
>> Ok, I'll grant that point. I would still say that it's not really an
>> accurate way of describing things when your 'bus' is connecting one
>> half of a die to the other half of the die, but I suppose it is still
>> a 'bus' of sorts, and certainly would be on the "backside" (relative
>> to memory).
>
> Why? There are *loads* of busses on processor chips, though most are
> driven from a single end (bi-di gets messy). ...right down to the
> power busses, though sometimes they're grids. ;-)
>
> --
> Keith

And people talk about the power bus even when it is a grid. Just like
they talk about the clock tree when it is a grid. And real designers
sometimes talk about the HT bus or the RIO bus, or the GX bus even when
it is a link more than a bus.

del
Anonymous
a b à CPUs
September 10, 2005 11:21:36 PM

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On Sat, 10 Sep 2005 07:37:13 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote:

>It calls it a bus (a Front Side bus at that) in the portion you snipped
>out and you know it. I don't know why you cut it out. it only makes you
>look trollish. Here's some more info for you.
>
>http://www.free-definition.com/Front-side-bus.html

Hmm, from this link, at the bottom of the chart:

"*** - Athlon 64, FX, and Opteron processors have a memory controller
on the CPU die, which replaces the traditional FSB"

>http://www.free-definition.com/category/Computer_bus

Try this one:

http://www.free-definition.com/Computer-bus.html

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

Hypertransport is a point-to-point connection, as is PCI-Express.
GTL+ and PCI are buses.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 10, 2005 11:21:36 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sat, 10 Sep 2005 08:33:53 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote:

>On Fri, 09 Sep 2005 23:18:00 -0400, keith wrote:
>> There is no such "proof". The definition of a "bus" is much older than
>> even you. A buss is a multi-drop utility. ...kinda like what you take to
>> work. A point-to-point facility is never referred to as a "bus".
>>
>You wouldn't know the definition if it bit you on the ass. But, just to
>show how stupid this response is, the frontside bus was point to point, as
>was the back side bus. The same could be said for the memory bus. IOW's
>you don't know wtf you are talking about.

Uhh ?!?! The GTL bus used in the PPro was DEFINTIELY a multi-point
bus. You can hang up to 4 CPUs off of that bus. This is still true
(at least in some situations) for the AGTL+ bus that Intel still uses
for their P4 and Xeon CPUs.

Similarly the backside bus in the PPro, PII and early PIII chips could
definitely have more than one memory device hung off the back of it.
If my memory is serving me, some Xeon CPUs had up to 4 cache chips on
a single bus. You can't do that with a point-to-point link!

Keeping up with the memory bus it DEFINITELY is a multidrop bus with
only one popular exception that I'm aware of (RDRAM). How else do you
think you can hang more than one DIMM off a single memory bus?

EV6, on the other hand, was not a bus by the strict multidrop
definition of things in that you could NOT hang more than one
processor off the bus. That's why AthlonMP systems (and DEC/Compaq/HP
Alpha systems before it) had one bus per processor. This is a large
part of the reason why you never saw quad AthlonMP systems, only dual
processor ones. Now, that being said, EV6 resembled a bus in most
other respects, which is why I said that it kind of blurred the lines
between a traditional bus and a strictly point-to-point connection.


Now, just how strictly one follows some of these definitions of what a
"bus" is depends on the reader. I know many people (myself included)
would tend to take shortcuts most of the time. Generally speaking I
would quite freely refer to EV6 as a "bus" rather than going through
the above explanation. I'm sure I've even been known to call
PCI-Express or Hypertransport a "bus" from time to time, though I
still recognize that it's not correct.


>9. How does HyperTransport technology compare to other bus technologies?
>
>*this is the relevent part*
>HyperTransport was designed to support both CPU-to-CPU communications as
>well as CPU-to-I/O transfers, thus, it features very low latency.
>Consequently, it has been incorporated into multiple x86 and MIPS
>architecture processors as an integrated front-side bus.

That's rather poorly worded on their part and actually contradicts
other parts of the same article where they (correctly) state that
Hypertransport is not a bus at all. As mentioned above though, people
take shortcuts, sometimes even when they know it's not really correct.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
September 11, 2005 12:11:55 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sat, 10 Sep 2005 11:29:47 -0500, Del Cecchi wrote:

>
> "keith" <krw@att.bizzzz> wrote in message
> news:p an.2005.09.10.14.25.43.450875@att.bizzzz...
>> On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:
>>
>>> On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:
>>>
>>>>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>>>>
>>>>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>>>>> <w.newell@TAKEOUTverizon.net> wrote:
>>>>>
>>>>> Not true at all. The original AMD Athlon had both a front-side bus,
>>>>> connecting the CPU to the chipset, I/O and memory, and a backside
>>>>> bus
>>>>> that connected the CPU to the cache chips on the Slot-A cartridge.
>>>>> This was actually the last x86 CPU that I'm aware of which did have
>>>>> a
>>>>> frontside bus (Intel had already gone to integrated cache by this
>>>>> time).
>>>>
>>>>Just because the cache is integrated doesn't mean the cache isn't on
>>>>the
>>>>"back side" of the processor. The "back-side" concept was really a
>>>>separation of the cache from the memory busses.
>>>
>>> Ok, I'll grant that point. I would still say that it's not really an
>>> accurate way of describing things when your 'bus' is connecting one
>>> half of a die to the other half of the die, but I suppose it is still
>>> a 'bus' of sorts, and certainly would be on the "backside" (relative
>>> to memory).
>>
>> Why? There are *loads* of busses on processor chips, though most are
>> driven from a single end (bi-di gets messy). ...right down to the
>> power busses, though sometimes they're grids. ;-)
>>
>> --
>> Keith
>
> And people talk about the power bus even when it is a grid. Just like
> they talk about the clock tree when it is a grid. And real designers
> sometimes talk about the HT bus or the RIO bus, or the GX bus even when
> it is a link more than a bus.

People call cyan, blue too. Because people get sloppy, doesn't change the
meaning of words. In technical writing, words do have meanings.

--
Keith
>
> del
Anonymous
a b à CPUs
September 11, 2005 12:30:00 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

"keith" <krw@att.bizzzz> wrote in message
news:p an.2005.09.11.00.11.52.492583@att.bizzzz...
> On Sat, 10 Sep 2005 11:29:47 -0500, Del Cecchi wrote:
>
>>
>> "keith" <krw@att.bizzzz> wrote in message
>> news:p an.2005.09.10.14.25.43.450875@att.bizzzz...
>>> On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:
>>>
>>>> On Fri, 09 Sep 2005 11:29:38 -0400, keith <krw@att.bizzzz> wrote:
>>>>
>>>>>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>>>>>
>>>>>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>>>>>> <w.newell@TAKEOUTverizon.net> wrote:
>>>>>>
>>>>>> Not true at all. The original AMD Athlon had both a front-side
>>>>>> bus,
>>>>>> connecting the CPU to the chipset, I/O and memory, and a backside
>>>>>> bus
>>>>>> that connected the CPU to the cache chips on the Slot-A cartridge.
>>>>>> This was actually the last x86 CPU that I'm aware of which did
>>>>>> have
>>>>>> a
>>>>>> frontside bus (Intel had already gone to integrated cache by this
>>>>>> time).
>>>>>
>>>>>Just because the cache is integrated doesn't mean the cache isn't on
>>>>>the
>>>>>"back side" of the processor. The "back-side" concept was really a
>>>>>separation of the cache from the memory busses.
>>>>
>>>> Ok, I'll grant that point. I would still say that it's not really
>>>> an
>>>> accurate way of describing things when your 'bus' is connecting one
>>>> half of a die to the other half of the die, but I suppose it is
>>>> still
>>>> a 'bus' of sorts, and certainly would be on the "backside" (relative
>>>> to memory).
>>>
>>> Why? There are *loads* of busses on processor chips, though most are
>>> driven from a single end (bi-di gets messy). ...right down to the
>>> power busses, though sometimes they're grids. ;-)
>>>
>>> --
>>> Keith
>>
>> And people talk about the power bus even when it is a grid. Just like
>> they talk about the clock tree when it is a grid. And real designers
>> sometimes talk about the HT bus or the RIO bus, or the GX bus even
>> when
>> it is a link more than a bus.
>
> People call cyan, blue too. Because people get sloppy, doesn't change
> the
> meaning of words. In technical writing, words do have meanings.
>
> --
> Keith
Well, you wanna be picky, cyan is blue. And taupe is tan. And a link is
a bus. Just a special case is all. Just what is the difference? If I
only have two pins on a bus connection, like many PCI-X implementations,
does that make it not a bus?

I was just reporting what folks I hang around with during the week say.
What's the big deal? Saying HT is a link is more specific than saying it
is a bus, but I consider it to also be a bus. It's a floor wax and a
dessert topping.

del
Anonymous
a b à CPUs
September 11, 2005 9:25:33 AM

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On Sat, 10 Sep 2005 19:21:36 -0400, Tony Hill wrote:

> On Sat, 10 Sep 2005 07:37:13 GMT, Wes Newell
> <w.newell@TAKEOUTverizon.net> wrote:
>
>>It calls it a bus (a Front Side bus at that) in the portion you snipped
>>out and you know it. I don't know why you cut it out. it only makes you
>>look trollish. Here's some more info for you.
>>
>>http://www.free-definition.com/Front-side-bus.html
>
> Hmm, from this link, at the bottom of the chart:
>
> "*** - Athlon 64, FX, and Opteron processors have a memory controller
> on the CPU die, which replaces the traditional FSB"
>
Note the wording. It doesn't say it replaces the FSB. It says it replaces
the traditional FSB. The FSB is still there, jst not in a tradidtional
sense, since the memory has it's own path now. I'll tell you what. You can
call it whatever you like, and I'll do the same.

>>http://www.free-definition.com/category/Computer_bus
>
> Try this one:
>
> http://www.free-definition.com/Computer-bus.html
>
> "In computer architecture, a bus is a subsystem that transfers data or
> power between computer components inside a computer or between
> computers. Unlike a point-to-point connection, a bus can logically
> connect several peripherals over the same set of wires."
>
But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)? And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus? One sometimes one has to think logical rather than just take
something at face value.

> Hypertransport is a point-to-point connection, as is PCI-Express. GTL+
> and PCI are buses.
>
Along with HyperTransport, PCI-Express is also defined as a Computer bus.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm
Anonymous
a b à CPUs
September 11, 2005 5:52:36 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881
September 11, 2005 6:59:32 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald
<fammacd=!SPAM^nothanks@tellurian.com> wrote:

....snip...
>If we allow a bit of slack and call the on-die L2 cache connection a BSB,
>we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
>all it carries the same traffic as a FSB. AMD has used this terminology
>for its K7 architecture though some have argued with that. With the K8 the
>HT link to to the I/O sub-system, however, there is no CPU<-> memory
>traffic, which is the principal function of a FSB and is the derivation of
>the name; the up/down HT link doesn't even serve the same functions as a
>FSB.
>
....snip...

"no CPU<-> memory traffic"
Correct for uniprocessor system. As soon as we get to dual (trust me
on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
HT starts carrying CPU<-> memory traffic. It is especially true in
case of more than half dual Opty board out there (including mine)
where all RAM is hanging off one CPU, and the other accesses it
through HT.

NNN
Anonymous
a b à CPUs
September 11, 2005 8:27:26 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sun, 11 Sep 2005 05:25:33 GMT, Wes Newell
<w.newell@TAKEOUTverizon.net> wrote:

>> "In computer architecture, a bus is a subsystem that transfers data or
>> power between computer components inside a computer or between
>> computers. Unlike a point-to-point connection, a bus can logically
>> connect several peripherals over the same set of wires."
>>
>But if you use this definition, there was never a FSB, or BSB bus
>as these were both point to point connections. Was not the FSB of the
>original Pentium Pro point to point (cpu to chipset)?

No it most definitely was not. You could hang up to 4 PPro processors
off the same bus.

> And this defintition
>also disagrees with lots of other definitions of bus, and lastly, if my
>system has only one memory slot, does that mean my system doesn't have a
>memory bus?

If you're using SDRAM or DDR SDRAM then the bus connects to each
individual chip on the module. Unless you've only got a single memory
chip on your single DIMM then this is definitely not a direct
point-to-point connection.

Besides, it's more a question of what the bus is capable of, not so
much what it is actually being used for. Just because the P4
processor itself is only capable of working in a single-processor
setup doesn't change the fact that the AGTL+ bus that it uses can be
used for up to 4 processors on the same bus (as seen in some Xeon
systems).

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
Anonymous
a b à CPUs
September 12, 2005 3:33:38 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig wrote:

> Since there is no FSB to use as a reference for the CPU-core's
> clockspeed (as well as some of the other clocks), we need something else
> to provide the required reference clock signal.
>
> The solution to this problem is a 200MHz base-clock provided to the
> processor by the on-board clock-generator on all 8th-Generation
> platforms.
>
And that's exactly how previous generations platforms did it too.:-)

> This Article will explain how clocks are generated on an AMD
> 8th-Generation platform.
> http://forums.amd.com/index.php?showtopic=55881

This is a great article, but there's really no difference in the system
clock source of the K7 and K8. They both use the clkin signals. Previously
this clock was called FSB frequency or FSB clock or whatever a board
manufacurer wanted to use to set the clock generator. I think most used
FSB Frequency, but I haven't looked at all the boards bioses. So now comes
the K8 and in their wisdom (or lack of it IMO), thee decide the new bus
type of HT link shouldn't use FSB as the name like the previous K7 EV6
type bus. And that would have been fine if they would come up with another
name to set this clock. I haven't looked at many K8 boards, but it's
designated as System Bus in my bios. The big problem with that name is
that a system bus can any in the system, and isn't specific enough. Same
goes for HT link, which is really a name for a technology like EV6 is, and
is used in many applications than just the K8 CPU's. Not to mention there
can be multiple HT links in a system, so how do you know which one they're
talking about unless it spelled out. Looking back, it would have been
much better to use something like System Clock Gen or CPU Clock Gen for
this setting rather than FSB, but since we were shouldered with FSB, it
finally became known as the connection between the CPU and chipset, which
in fact it is, and that this was the setting to chnage to set the internal
cpu clock... Now that there's no FSB designated for the K8, there's also
no desgination one would easily recognize. So did AMD do away with the
FSB, or just the name because they wanted more exposure for HT or some
other reason. I contend, it was just the name they wanted to change since
the actual traces on the MB still go from the CPU to the chipset just like
previous FSB's with the exception of the memory bus. Had they keep the FSB
name, or even called it the HT FSB, there wouldn't have been the confusion
there is now. Fankly I don't care much. But since many peole don't like
the term FSB used with the K8, I'm going to start telling people to raise
the clkin frequency to the cpu to set the cpu speed and let them worry
about what there board maker called it in the bios. Now since the FSB
term was used to set clkin on previous cpu's, why is it now all of a
sudden taboo?

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm
September 12, 2005 4:30:13 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

"Tony Hill" <hilla_nospam_20@yahoo.ca> wrote in message
news:m349i152drvnh2b4l5tjkojpn7dce1lleu@4ax.com...
> On Sun, 11 Sep 2005 05:25:33 GMT, Wes Newell
> <w.newell@TAKEOUTverizon.net> wrote:
>
>>> "In computer architecture, a bus is a subsystem that transfers data or
>>> power between computer components inside a computer or between
>>> computers. Unlike a point-to-point connection, a bus can logically
>>> connect several peripherals over the same set of wires."
>>>
>>But if you use this definition, there was never a FSB, or BSB bus
>>as these were both point to point connections. Was not the FSB of the
>>original Pentium Pro point to point (cpu to chipset)?
>
> No it most definitely was not. You could hang up to 4 PPro processors
> off the same bus.
>
>> And this defintition
>>also disagrees with lots of other definitions of bus, and lastly, if my
>>system has only one memory slot, does that mean my system doesn't have a
>>memory bus?
>
> If you're using SDRAM or DDR SDRAM then the bus connects to each
> individual chip on the module. Unless you've only got a single memory
> chip on your single DIMM then this is definitely not a direct
> point-to-point connection.
>
> Besides, it's more a question of what the bus is capable of, not so
> much what it is actually being used for. Just because the P4
> processor itself is only capable of working in a single-processor
> setup doesn't change the fact that the AGTL+ bus that it uses can be
> used for up to 4 processors on the same bus (as seen in some Xeon
> systems).
>

You guys must be a barrel of laughs down the pub.... ;-)

Could ya knock of the non-technical game group from future posts pls?
Anonymous
a b à CPUs
September 12, 2005 5:21:57 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

Bobby

"Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
news:p an.2005.09.11.23.37.45.362968@TAKEOUTverizon.net...
> On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig wrote:
>
>> Since there is no FSB to use as a reference for the CPU-core's
>> clockspeed (as well as some of the other clocks), we need something else
>> to provide the required reference clock signal.
>>
>> The solution to this problem is a 200MHz base-clock provided to the
>> processor by the on-board clock-generator on all 8th-Generation
>> platforms.
>>
> And that's exactly how previous generations platforms did it too.:-)
>
>> This Article will explain how clocks are generated on an AMD
>> 8th-Generation platform.
>> http://forums.amd.com/index.php?showtopic=55881
>
> This is a great article, but there's really no difference in the system
> clock source of the K7 and K8. They both use the clkin signals. Previously
> this clock was called FSB frequency or FSB clock or whatever a board
> manufacurer wanted to use to set the clock generator. I think most used
> FSB Frequency, but I haven't looked at all the boards bioses. So now comes
> the K8 and in their wisdom (or lack of it IMO), thee decide the new bus
> type of HT link shouldn't use FSB as the name like the previous K7 EV6
> type bus. And that would have been fine if they would come up with another
> name to set this clock. I haven't looked at many K8 boards, but it's
> designated as System Bus in my bios. The big problem with that name is
> that a system bus can any in the system, and isn't specific enough. Same
> goes for HT link, which is really a name for a technology like EV6 is, and
> is used in many applications than just the K8 CPU's. Not to mention there
> can be multiple HT links in a system, so how do you know which one they're
> talking about unless it spelled out. Looking back, it would have been
> much better to use something like System Clock Gen or CPU Clock Gen for
> this setting rather than FSB, but since we were shouldered with FSB, it
> finally became known as the connection between the CPU and chipset, which
> in fact it is, and that this was the setting to chnage to set the internal
> cpu clock... Now that there's no FSB designated for the K8, there's also
> no desgination one would easily recognize. So did AMD do away with the
> FSB, or just the name because they wanted more exposure for HT or some
> other reason. I contend, it was just the name they wanted to change since
> the actual traces on the MB still go from the CPU to the chipset just like
> previous FSB's with the exception of the memory bus. Had they keep the FSB
> name, or even called it the HT FSB, there wouldn't have been the confusion
> there is now. Fankly I don't care much. But since many peole don't like
> the term FSB used with the K8, I'm going to start telling people to raise
> the clkin frequency to the cpu to set the cpu speed and let them worry
> about what there board maker called it in the bios. Now since the FSB
> term was used to set clkin on previous cpu's, why is it now all of a
> sudden taboo?
>
> --
> KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
> Need good help? Provide all system info with question.
> My server http://wesnewell.no-ip.com/cpu.php
> Verizon server http://mysite.verizon.net/res0exft/cpu.htm
>
Anonymous
a b à CPUs
September 12, 2005 7:18:41 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig <big_pig@farming.com> wrote:

>Since there is no FSB to use as a reference for the CPU-core's
>clockspeed (as well as some of the other clocks), we need something else
>to provide the required reference clock signal.
>
>The solution to this problem is a 200MHz base-clock provided to the
>processor by the on-board clock-generator on all 8th-Generation
>platforms.
>
>This Article will explain how clocks are generated on an AMD
>8th-Generation platform.
>http://forums.amd.com/index.php?showtopic=55881

This one doesn't have any mistakes:-) -
http://www.amd.com/us-en/assets/content_type/white_pape...

--
Rgds, George Macdonald
Anonymous
a b à CPUs
September 12, 2005 7:18:41 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Sun, 11 Sep 2005 14:59:32 GMT, "nobody@nowhere.net"
<mygarbage2000@hotmail.com> wrote:

>On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald
><fammacd=!SPAM^nothanks@tellurian.com> wrote:
>
>...snip...
>>If we allow a bit of slack and call the on-die L2 cache connection a BSB,
>>we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
>>all it carries the same traffic as a FSB. AMD has used this terminology
>>for its K7 architecture though some have argued with that. With the K8 the
>>HT link to to the I/O sub-system, however, there is no CPU<-> memory
>>traffic, which is the principal function of a FSB and is the derivation of
>>the name; the up/down HT link doesn't even serve the same functions as a
>>FSB.
>>
>...snip...
>
>"no CPU<-> memory traffic"
>Correct for uniprocessor system. As soon as we get to dual (trust me
>on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
>HT starts carrying CPU<-> memory traffic. It is especially true in
>case of more than half dual Opty board out there (including mine)
>where all RAM is hanging off one CPU, and the other accesses it
>through HT.

Of course but that's really CPU<->CPU traffic... which is why I made a
point of clearly specifying the "HT link to the I/O sub-system". Lifting
quoted text out of context only confuses the issue.

--
Rgds, George Macdonald
Anonymous
a b à CPUs
September 12, 2005 10:07:42 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:

> Your entire premise is wrong.
>
> Hypertransport is a High speed, packet based control and communication
> protocol. It supports the Direct Connect Architecture of the AMD Athlon64
> and Turion64 processors. The processor does not use the Northbridge to
> communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
> traditional Northbridge legacy set is handled by the chip, as is the
> Southbridge, but for the Proc, RAM and video there is no FSB, just the
> speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
> communication is duplex under Hypertransport, versus simplex under NB-FSB.
>
You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm
Anonymous
a b à CPUs
September 12, 2005 10:58:58 AM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

On Mon, 12 Sep 2005 06:07:42 GMT, Wes Newell <w.newell@TAKEOUTverizon.net>
wrote:

>On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:
>
>> Your entire premise is wrong.
>>
>> Hypertransport is a High speed, packet based control and communication
>> protocol. It supports the Direct Connect Architecture of the AMD Athlon64
>> and Turion64 processors. The processor does not use the Northbridge to
>> communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
>> traditional Northbridge legacy set is handled by the chip, as is the
>> Southbridge, but for the Proc, RAM and video there is no FSB, just the
>> speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
>> communication is duplex under Hypertransport, versus simplex under NB-FSB.
>>
>You're just a little more than confused. The CPU doesn't support AGP, PCI,
>PCI-E or much of anything else except the ram directly. The rest still are
>still functions of the chipset. The only thing that the CPU now supports
>directly is the memory. All other system devices/buses are handled the
>same way as the K7 was, over the FSB, or if you prefer, the HT Link
>between the cpu and chipset.

You have just proved your complete misunderstanding of what is on the K8
die and what the HT I/O-link is used for. All CPU memory accesses mapped
to I/O devices, such as AGP/PCI-e, or any PCI device must be trapped in the
CPU's "north bridge" sub-set and diverted to the HT I/O link; obviously the
corresponding MTRRs and associated logic *must* be on the CPU die. Same
for CPU cache snooping - previously a north bridge/FSB function and now
incorporated into the CPU.

Apart from CPU I/O reads/writes and interrupts, a minor part of FSB traffic
"volume", the HT I/O link has nothing in common with a FSB. The major
volume of traffic on the K8 HT I/O-link, viz. DMA transfers, is handled and
routed internally in the north bridge (MC Hub) of a FSB type system.

--
Rgds, George Macdonald
Anonymous
a b à CPUs
September 12, 2005 12:39:27 PM

Archived from groups: comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.ibm.pc.games.action (More info?)

"Wes Newell" <w.newell@TAKEOUTverizon.net> wrote in message
news:p an.2005.09.12.06.11.55.449547@TAKEOUTverizon.net...
> On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:
>
>> Your entire premise is wrong.
>>
>> Hypertransport is a High speed, packet based control and communication
>> protocol. It supports the Direct Connect Architecture of the AMD
>> Athlon64
>> and Turion64 processors. The processor does not use the Northbridge to
>> communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there.
>> The
>> traditional Northbridge legacy set is handled by the chip, as is the
>> Southbridge, but for the Proc, RAM and video there is no FSB, just the
>> speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition,
>> the
>> communication is duplex under Hypertransport, versus simplex under
>> NB-FSB.
>>
> You're just a little more than confused. The CPU doesn't support AGP, PCI,
> PCI-E or much of anything else except the ram directly. The rest still are
> still functions of the chipset. The only thing that the CPU now supports
> directly is the memory. All other system devices/buses are handled the
> same way as the K7 was, over the FSB, or if you prefer, the HT Link
> between the cpu and chipset.
>
> --
> KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
> Need good help? Provide all system info with question.
> My server http://wesnewell.no-ip.com/cpu.php
> Verizon server http://mysite.verizon.net/res0exft/cpu.htm
>
Re-read what I wrote...I did not say that it did, but that the
hypertransport bus allows greater bandwidth and duplex operations. The
memory controller accesses the cache and RAM data.
The NB is legacy, while the SB still functions in a traditional manner.

Bobby
!