Archived from groups: alt.comp.periphs.mainboard.asus (
More info?)
Thanx a billion - but the strange thing is that my memory (2x 256 MB Crucial
PC-2100 CL 2.5) already ran flawlessly on my 1st P4G8X DLX - even in dual
mode and @ 166 MHz clock with manual CL2 timing. I replaced them by Kingston
PC-3200 when I upgraded from a P4 1600 (FSB 400) to a P4 2800 (FSB 800) -
the P4G8X handles FSB speeds up to 189 MHz rock stable, so the loss was not
too big.
But in the "new" P4G8X - nada. Beep---Beep---Beep---Beep..... :-((((
"Paul" <nospam@needed.com> wrote in message
news:nospam-0406040150350001@192.168.1.177...
> In article <ni5vb0d99eigrtscdmdq9c49h63g85f8i1@4ax.com>, deeze@nutz.com
wrote:
>
> > pull up the manual on the asus website and look up the error beep code
> >
> > On Thu, 3 Jun 2004 23:03:44 +0200, "Joachim Klein"
> > <jvklein@t-online.de> wrote:
> >
> > >Hi folks,
> > >
> > >ferengi rule of acquisition: if something seems to nice to be true it
often
> > >is so...
> > >Well - I got a P4G8X DLX for very, very decent 40 bucks. After
installing
> > >CPU, AGP-card and so on I tried to start the machine but all I got was
an
> > >endless sequence of long beeps with a 2 second pause.
> > >Any idea what this means ?
> > >CPU defect ? Memory defect ?
> > >
> > >Thanx a billion in advance for your input !
> > >
> > >Cya -
> > >
> > >Joachim
> > >
>
> See section 2.5.2 of the manual. P4G8X uses unbuffered memory, and
> if using one stick of memory, the manual says to use slot A2.
>
> The Northbridge datasheet is here:
>
http://www.intel.com/design/chipsets/e7205/datashts/25193702.pdf
>
> It says:
>
> "Memory Operation
> The MCH contains a dual channel DDR interface, with each channel
> having 64 data bits and 8 ECC bits. The memory interface operates
> in ³lock-step² with each other. The data is a double QWord
> interleaved between the channels with the low DQWord on channel A
> and the high DQWord on channel B. A burst of four data items, that
> take two clocks, is required for one cache line (64 bytes). A
> 256-bit interface transfers the data at the core clock frequency
> internally, matching the memory bandwidth. The memory must be
> populated in identical DIMM configurations (i.e., Slot 0 of channel
> A must contain the same configuration DIMM as Slot 0 of channel B).
> The configuration consists of the same number of rows (1 or 2), the
> same technology part (128 Mb, 256 Mb, 512 Mb), the same DRAM chip
> width (x8, or x16), and the same speed."
>
> so if using more than one stick, you would be advised to match the
> memory on each channel. It is hard to say, but the controller on
> this board may not be as flexible as an 865/875 board, which has
> what is called virtual single channel mode, for use with non
> matching memory DIMMs.
>
> HTH,
> Paul
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