Archived from groups: alt.comp.periphs.mainboard.asus (
More info?)
In article <f57ef644.0408200425.3e61f621@posting.google.com>,
sam.vanratt@gmx.net (sam.vanratt) wrote:
> Hi Paul,
> I solved it in the meantime by installing a "pullup" R (45,5k/.5% T)
> from +5V to FB pin and getting a clean 1.004V output (using a resistor
> array for exoerimenting), while setting the VID1-5 to 01111 to get a
> min. of 1.100V. Pourly the BIOS don't allow to boot up then. I tried
> all three A7N8X-E Deluxe, A7N8X-X and A7N8X-E with this (all have a
> nearly identical BIOS). They work good after using a standard e.g XP
> Barton (after putting the VRM to standard). My hope was to use an
> NVidia based board instead of the K400VM we already using. Upgrading
> the BIOS to 1010 didn't help either.
> Anyway the Geode is the best CPU I've seen in years (The P-M was quite
> nice before). It outperforms it VIA C3 rival by far and even consums
> less power. But same as P4M: it has different (incompatible) VID and
> CPU-ID.
> Thanks for your reply it gave me the right direction. The pic'd have
> helped me to find out how we reenginered the A7V8X without having one
> at hand.
> Cheers
> Sam
There are some things you could try:
First off, I traced an Asus motherboard a while back, and found
a circuit that looks like this:
---------- -------- VID ---------------
|processor|---|series |-------+------------|Vcore regulator
|VID pins |---|resistor|---------+----------|chip
---------- -------- | | ---------------
| |
-----------
| SuperI/O |
| overrides |
| VID |
-----------
^ ^
| |
BIOS programming
Basically, the idea is, the Super I/O chip has some GPIO pins
that are tristated at powerup. The logic 0 or 1 value from the
processor VID pins propagates to the Vcore regulator. The
processor receives its nominal voltage just after reset is
deasserted. The series resistors give the processor "weak"
control over the VID signals.
If the user enters the BIOS and changes the VID code from the
default, then the Super I/O chip enables the drivers on the
GPIO pins, and the BIOS then has control of the VID values.
The GPIO driver strength is sufficient to override the
processor VID code.
So, for absolute control over VID, bend up the VID pins on
the Vcore regulator chip, and hardwire logic 0 or logic 1
directly to the Vcore regulator. That will prevent the BIOS
from changing things on you.
Secondly, with an AthlonXP in the socket, enter the BIOS
and disable Vcore monitoring. It should be in the hardware
monitor page, and maybe if you select [disable] for Vcore,
the processor won't react to the abnormally low Vcore.
If this still doesn't work, trace the Vcore voltage signal
which is fed to the hardware monitor chip. Clip one probe
of the ohmmeter, to the Vcore copper plane around the
processor socket. Do a "lap of the pins" of the ASB100 with
the ohmmeter, looking for a pin that is connected to Vcore.
The magnitude of Vcore is low enough, that a voltage divider
network is not likely to be used in the path from Vcore.
If you can manage to find where the ASB100 monitors Vcore,
then bend up that pin, and make a two resistor voltage divider,
and tie the top of the divider to +3.3V. Select resistors to
give 1.65V, which could be a couple of 1K ohm resistors if you
want. By doing that, you will "blind" the BIOS, so it cannot
sense the abnormally low voltage.
The only other issue would be the Vcore regulator itself. It
has internal detection of out of range voltage, so be careful
to not overdo it with the FB resistor. I would try setting 1.1V
directly to the VID pins on the regulator, and not bother using
FB, until you can get the BIOS sufficiently "blind" so it
won't stop the booting.
It is also possible the voltage is not an issue, and the Geode
just isn't recognized by the BIOS as a valid processor.
HTH,
Paul
>
> nospam@needed.com (Paul) wrote in message
news:<nospam-1308041943350001@192.168.1.177>...
> > In article <f57ef644.0408130205.63280b49@posting.google.com>,
> > sam.vanratt@gmx.net (sam.vanratt) wrote:
> >
> > > Hi folks,
> > > I need to get my Vcc down to 1.00V on an A7N8X-X by biasing the FB
> > > path of the used ST controller. I alread got a working version on an
> > > A7V8-MX SE, but couldn't disassemble it any more to take a closer look
> > > at the circuit layout. A hiRes pic of the A7V8 mobo VRM (a richtek
> > > 9241b) would suffice to get a step further. Did anyone tempered with
> > > the VRM L6917B directly. As I need it fast I cannot get an eva board
> > > fast enough from ST directly to probe with it instead of defecting
> > > mobos.
> > > Cheers
> > > Sam
> >
> > First off, I'm not a power supply designer, so take all this with
> > a grain of salt.
> >
> > To control the output, you would need to source or sink current from
> > the FB terminal. Why would you need layout info ? Either you are
> > connecting a new resistor between FB and GND or connecting a new
> > resistor between "a regulated voltage higher than VID" and FB.
> >
> > In the circuit schematic provided in the L6917B datasheet, I
> > don't think R9 is normally populated. R9 might not even be
> > present in the schematic for the motherboard circuit.
> >
> > The safest way to modify a Vcore circuit, is to reprogram the VID
> > pins. In this case you can get 1.1V using VID=11110, but you
> > already know that. If you make a mistake while adjusting via
> > FB, the voltage can shoot up. Since the L6917B has OV and
> > UV protection, it will stop the circuit at some point.
> >
> > Paul
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