single sided vs. double sided, how to tell?

Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

How do I know, by vendor description, if a RAM stick is single sided (chips
only on one side) vs. double sided?

Are there advantages to getting single sided vs. double sided?

TIA

~signmeuptoo
9 answers Last reply
More about single sided double sided tell
  1. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    In article <1or91nmf92fl9$.i7si8vc1pwwi$.dlg@40tude.net>,
    signmeuptoo@earthlink.net wrote:

    > How do I know, by vendor description, if a RAM stick is single sided (chips
    > only on one side) vs. double sided?
    >
    > Are there advantages to getting single sided vs. double sided?
    >
    > TIA
    >
    > ~signmeuptoo

    In most cases, there is too little info available, to know what
    you are buying. Especially with the cheaper generic RAM.

    With Crucial, you take the Crucial part number, find a picture of
    the Crucial module on Newegg, get the Micron part number off the
    picture of the sticker, and then download a datasheet from Micron
    (they have a section devoted to their modules and to the chips
    they make). I have never seen a cross reference table, that
    converts a Crucial part number, into the Micron module used
    for that purpose.

    With Kingston, datasheet download links are available on the
    product description page.

    For Corsair, you can go to corsairmicro.com and download a
    datasheet from their product listings.

    Samsung also has datasheets:
    http://www.samsung.com/Products/Semiconductor/common/product_list.aspx?family_cd=DRM030202

    Those are all the ones I know of, or have searched for.

    Crucial gives a hint, by putting "-8T" or "-16T" on the end
    of the part number, but not all adverts include that info.

    In terms of construction, a bank of RAM is any number of
    chips put side-by-side, to build a 64 bit wide array of memory.
    The most popular widths of memory chips are 8 bits and 16 bits.
    That means you could construct an array with four or eight
    chips. (It is irrelevant, but I believe I've seen 2,4,8,16, and
    32 bit wide chips, but some of those are used for more obscure
    purposes. I have a x32 chip, for example, on a Xilinx development
    board.) When you find 8 chips on a module, it could be (8) (x8)
    chips or it could be two groups of (4) (x16) chips.

    So, what is relevant about banks of RAM ? In the case of FPM, EDO,
    SDRAM, DDR, DDR2, all the chips on the module load down the address
    bus. A module with 16 chips puts 16 loads on the address bus.
    A module with 8 chips puts 8 loads on the address bus. Each load
    has a certain input capacitance. A capacitor stores
    electrical charge, and the more you've got, the harder it is to
    wiggle the signal on the line up and down. What that means, is
    a DIMM with fewer chips on it, can be run at a higher speed if you
    are overclocking. So, what you really want, is a module with as
    few chips as possible, for the highest operating speed. But of
    course, a module with few chips on it, gives you less total memory.
    For overclockers, two single sided 256MB DIMMs, run in dual
    channel, is a typical overclocking config, but few people
    are really happy with only 512MB total RAM. If RAM chips of
    32Mx16 were used, you could build that module with four chips.

    Registered memory gets around this, as a register (buffer) chip
    on the DIMM, forms an intermediate stopping point for the signals.
    The address bus from the motherboard only drives the register chip,
    then the register chip drives the 8 or 16 or 32 memory chips. The
    register chip increases the latency in getting to the module, so
    peformance drops due to that, but the advantage is, that many more
    DIMMs can be driven, before the address bus runs out of drive
    strength. That is why server boards can have larger arrays of
    DIMMs. But, as an overclocker, I doubt a registered DIMM would
    make a good candidate for overclocking, as the register chip
    has frequency limits to it that are likely tighter than
    a memory chip.

    At the densities most people are interested in, modules will
    have eight or sixteen chips. Now that larger chips are available,
    it is possible to find single bank eight chip 512MB modules,
    which cause less loading than a double bank sixteen chip 512MB
    module (that is the commodity configuration). Usually the
    price will be an indicator of what you are getting.

    For example, the first Crucial module here, uses 64Mx8 chips,
    and the second module uses 32Mx8 chips. Per 512MB worth of
    memory, the first module is 50% more expensive. If the first
    (1GB) module was half populated, with only eight chips, it
    would give 512MB of RAM, with half the electrical load on
    the address bus, of the second module.

    1GB ‹ CT12864Z40B DDR PC3200 CL=3 NON-ECC UNBUFFERED $181.99
    512MB ‹ CT6464Z40B DDR PC3200 CL=3 NON-ECC UNBUFFERED $ 59.99

    In order to buy and use 512MB single sided DIMMs, your motherboard
    manual has to claim support for 1GB modules. This has to do with
    support for the memory chip size, rather than the module itself.
    As the chips are the same 64Mx8 on a 512MB single sided and a 1GB
    double sided DIMM, the row and column address signals are the
    same.

    I hope that isn't too confusing. With all the rows, columns,
    banks, and ranks on DIMMs, it is hard to keep track of all
    the issues.

    Paul
  2. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    Paul wrote:
    > the more you've got, the harder it is to
    > wiggle the signal on the line up and down.

    <SNIP>

    > I hope that isn't too confusing.

    <SNIP>

    :-)

    Jokes aside, that was an excellent description.

    Ben
    --
    A7N8X FAQ: www.ben.pope.name/a7n8x_faq.html
    Questions by email will likely be ignored, please use the newsgroups.
    I'm not just a number. To many, I'm known as a String...
  3. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    Paul, could you please explain to me the ##Mx## thing? I mean, for
    instance, is a 64Mx8 mean there there is 8 chips of 64 Meg capacity? And
    then, does that description skip showing the X1 or X2 banks. Why then
    isn't memory described as, for instance 64Mx8x1 to designate a 512Meg stick
    and 64Mx8x2 used to describe a 1Gig stick? Why do they omit that last
    number?

    Am I correct in understanding what you are saying?

    Also, I know that DDR memory runs on both the rise *and* fall time of the
    clock cycles, but how does DDR3 of the latest Video RAM work?


    On Sat, 26 Mar 2005 12:54:58 -0500, Paul wrote:

    > In article <1or91nmf92fl9$.i7si8vc1pwwi$.dlg@40tude.net>,
    > signmeuptoo@earthlink.net wrote:
    >
    >> How do I know, by vendor description, if a RAM stick is single sided (chips
    >> only on one side) vs. double sided?
    >>
    >> Are there advantages to getting single sided vs. double sided?
    >>
    >> TIA
    >>
    >> ~signmeuptoo
    >
    > In most cases, there is too little info available, to know what
    > you are buying. Especially with the cheaper generic RAM.
    >
    > With Crucial, you take the Crucial part number, find a picture of
    > the Crucial module on Newegg, get the Micron part number off the
    > picture of the sticker, and then download a datasheet from Micron
    > (they have a section devoted to their modules and to the chips
    > they make). I have never seen a cross reference table, that
    > converts a Crucial part number, into the Micron module used
    > for that purpose.
    >
    > With Kingston, datasheet download links are available on the
    > product description page.
    >
    > For Corsair, you can go to corsairmicro.com and download a
    > datasheet from their product listings.
    >
    > Samsung also has datasheets:
    > http://www.samsung.com/Products/Semiconductor/common/product_list.aspx?family_cd=DRM030202
    >
    > Those are all the ones I know of, or have searched for.
    >
    > Crucial gives a hint, by putting "-8T" or "-16T" on the end
    > of the part number, but not all adverts include that info.
    >
    > In terms of construction, a bank of RAM is any number of
    > chips put side-by-side, to build a 64 bit wide array of memory.
    > The most popular widths of memory chips are 8 bits and 16 bits.
    > That means you could construct an array with four or eight
    > chips. (It is irrelevant, but I believe I've seen 2,4,8,16, and
    > 32 bit wide chips, but some of those are used for more obscure
    > purposes. I have a x32 chip, for example, on a Xilinx development
    > board.) When you find 8 chips on a module, it could be (8) (x8)
    > chips or it could be two groups of (4) (x16) chips.
    >
    > So, what is relevant about banks of RAM ? In the case of FPM, EDO,
    > SDRAM, DDR, DDR2, all the chips on the module load down the address
    > bus. A module with 16 chips puts 16 loads on the address bus.
    > A module with 8 chips puts 8 loads on the address bus. Each load
    > has a certain input capacitance. A capacitor stores
    > electrical charge, and the more you've got, the harder it is to
    > wiggle the signal on the line up and down. What that means, is
    > a DIMM with fewer chips on it, can be run at a higher speed if you
    > are overclocking. So, what you really want, is a module with as
    > few chips as possible, for the highest operating speed. But of
    > course, a module with few chips on it, gives you less total memory.
    > For overclockers, two single sided 256MB DIMMs, run in dual
    > channel, is a typical overclocking config, but few people
    > are really happy with only 512MB total RAM. If RAM chips of
    > 32Mx16 were used, you could build that module with four chips.
    >
    > Registered memory gets around this, as a register (buffer) chip
    > on the DIMM, forms an intermediate stopping point for the signals.
    > The address bus from the motherboard only drives the register chip,
    > then the register chip drives the 8 or 16 or 32 memory chips. The
    > register chip increases the latency in getting to the module, so
    > peformance drops due to that, but the advantage is, that many more
    > DIMMs can be driven, before the address bus runs out of drive
    > strength. That is why server boards can have larger arrays of
    > DIMMs. But, as an overclocker, I doubt a registered DIMM would
    > make a good candidate for overclocking, as the register chip
    > has frequency limits to it that are likely tighter than
    > a memory chip.
    >
    > At the densities most people are interested in, modules will
    > have eight or sixteen chips. Now that larger chips are available,
    > it is possible to find single bank eight chip 512MB modules,
    > which cause less loading than a double bank sixteen chip 512MB
    > module (that is the commodity configuration). Usually the
    > price will be an indicator of what you are getting.
    >
    > For example, the first Crucial module here, uses 64Mx8 chips,
    > and the second module uses 32Mx8 chips. Per 512MB worth of
    > memory, the first module is 50% more expensive. If the first
    > (1GB) module was half populated, with only eight chips, it
    > would give 512MB of RAM, with half the electrical load on
    > the address bus, of the second module.
    >
    > 1GB ‹ CT12864Z40B DDR PC3200 CL=3 NON-ECC UNBUFFERED $181.99
    > 512MB ‹ CT6464Z40B DDR PC3200 CL=3 NON-ECC UNBUFFERED $ 59.99
    >
    > In order to buy and use 512MB single sided DIMMs, your motherboard
    > manual has to claim support for 1GB modules. This has to do with
    > support for the memory chip size, rather than the module itself.
    > As the chips are the same 64Mx8 on a 512MB single sided and a 1GB
    > double sided DIMM, the row and column address signals are the
    > same.
    >
    > I hope that isn't too confusing. With all the rows, columns,
    > banks, and ranks on DIMMs, it is hard to keep track of all
    > the issues.
    >
    > Paul
  4. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    In article <1d16ez0qhors1$.18mvp8lahqdce$.dlg@40tude.net>,
    signmeuptoo@earthlink.net wrote:

    > Paul, could you please explain to me the ##Mx## thing? I mean, for
    > instance, is a 64Mx8 mean there there is 8 chips of 64 Meg capacity? And
    > then, does that description skip showing the X1 or X2 banks. Why then
    > isn't memory described as, for instance 64Mx8x1 to designate a 512Meg stick
    > and 64Mx8x2 used to describe a 1Gig stick? Why do they omit that last
    > number?
    >
    > Am I correct in understanding what you are saying?
    >
    > Also, I know that DDR memory runs on both the rise *and* fall time of the
    > clock cycles, but how does DDR3 of the latest Video RAM work?
    >

    64Mx8 means the silicon die has 512 megabits of RAM. A parallel
    bus of 8 bits in width, is used to read and write the memory in
    the chip. So, logically speaking, think of the memory as an
    array 64 million locations deep and 8 bits wide.

    Inside a typical memory chip, memory is broken into four arrays.
    Each array is "rows" x "columns" wide. The four separate
    arrays of memory are "banks". So, from a terminology perspective,
    that leaves "ranks", to describe the two banks of memory on a
    double sided DIMM.

    The internal organization of a memory chip, is only important
    when trying to figure out how big a memory chip that a
    Northbridge can support. Northbridges (or the integrated memory
    controller in an Athlon64/Opteron) have a limited number of
    address bits, to drive multiplexed row and column addresses to
    the memory chips. And, that is where the "density issue" comes
    in - when you can only see half the memory on a DIMM, it
    can be caused by a shortage of address bit from the memory
    controller interface.

    As for describing memory, a description of (16) 64Mx8 would be
    enough info to conclude a DIMM was double sided (two ranks). For
    reasons unknown to me, vendors refuse to describe it that way.
    After all, it is in their best interests, to provide as little
    info as possible about the shortcomings of any product.

    This will answer all your questions about GDDR3. One of the
    advantages of GDDR3, is reduced power consumption, due to
    the modified I/O used, and that is one of the reasons to look
    for it on a video card:

    http://download.micron.com/pdf/pubs/designline/dl402.pdf

    Paul
  5. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    On Mon, 28 Mar 2005 17:14:05 -0500, Paul wrote:

    > In article <1d16ez0qhors1$.18mvp8lahqdce$.dlg@40tude.net>,
    > signmeuptoo@earthlink.net wrote:
    >
    >> Paul, could you please explain to me the ##Mx## thing? I mean, for
    >> instance, is a 64Mx8 mean there there is 8 chips of 64 Meg capacity? And
    >> then, does that description skip showing the X1 or X2 banks. Why then
    >> isn't memory described as, for instance 64Mx8x1 to designate a 512Meg stick
    >> and 64Mx8x2 used to describe a 1Gig stick? Why do they omit that last
    >> number?
    >>
    >> Am I correct in understanding what you are saying?
    >>
    >> Also, I know that DDR memory runs on both the rise *and* fall time of the
    >> clock cycles, but how does DDR3 of the latest Video RAM work?
    >>
    >
    > 64Mx8 means the silicon die has 512 megabits of RAM. A parallel
    > bus of 8 bits in width, is used to read and write the memory in
    > the chip. So, logically speaking, think of the memory as an
    > array 64 million locations deep and 8 bits wide.
    >
    > Inside a typical memory chip, memory is broken into four arrays.
    > Each array is "rows" x "columns" wide. The four separate
    > arrays of memory are "banks". So, from a terminology perspective,
    > that leaves "ranks", to describe the two banks of memory on a
    > double sided DIMM.
    >
    > The internal organization of a memory chip, is only important
    > when trying to figure out how big a memory chip that a
    > Northbridge can support. Northbridges (or the integrated memory
    > controller in an Athlon64/Opteron) have a limited number of
    > address bits, to drive multiplexed row and column addresses to
    > the memory chips. And, that is where the "density issue" comes
    > in - when you can only see half the memory on a DIMM, it
    > can be caused by a shortage of address bit from the memory
    > controller interface.
    >
    > As for describing memory, a description of (16) 64Mx8 would be
    > enough info to conclude a DIMM was double sided (two ranks). For
    > reasons unknown to me, vendors refuse to describe it that way.
    > After all, it is in their best interests, to provide as little
    > info as possible about the shortcomings of any product.
    >
    > This will answer all your questions about GDDR3. One of the
    > advantages of GDDR3, is reduced power consumption, due to
    > the modified I/O used, and that is one of the reasons to look
    > for it on a video card:
    >
    > http://download.micron.com/pdf/pubs/designline/dl402.pdf
    >
    > Paul

    I think I understand, maybe. I took digital electronics in tech school,
    but didn't study RAM, didn't go that far, due to what they were training
    us.

    So what you mean is that there are 64 million transistors and the buss that
    transferrs the data to and from them is 8 bit across? So why is it that it
    so happens that 64 times 8 comes out to 512? Is that just a coincidence,
    or are there 8 different sets of 64 million transistors?

    Is there a site or video that you like to use to explain all of this?

    I am feeling pretty dumb right now, because I thought that I used to know
    how this works and I don't remember now.

    Also, do you happen to know how many layers deep these transistors go, and
    is that part of the equation?

    Would this mean that 128Mx8 mean that it was a 1 gig module? And then, if
    there was 64Mx4 it would be a 256Meg module? Would this second example use
    four chips?
  6. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    On Tue, 29 Mar 2005 03:07:40 GMT, signmeuptoo
    <signmeuptoo_no_spam@earthlink.net> wrote:

    >On Mon, 28 Mar 2005 17:14:05 -0500, Paul wrote:
    >
    >> In article <1d16ez0qhors1$.18mvp8lahqdce$.dlg@40tude.net>,
    >> signmeuptoo@earthlink.net wrote:
    >>
    >>> Paul, could you please explain to me the ##Mx## thing? I mean, for
    >>> instance, is a 64Mx8 mean there there is 8 chips of 64 Meg capacity? And
    >>> then, does that description skip showing the X1 or X2 banks. Why then
    >>> isn't memory described as, for instance 64Mx8x1 to designate a 512Meg stick
    >>> and 64Mx8x2 used to describe a 1Gig stick? Why do they omit that last
    >>> number?
    >>>
    >>> Am I correct in understanding what you are saying?
    >>>
    >>> Also, I know that DDR memory runs on both the rise *and* fall time of the
    >>> clock cycles, but how does DDR3 of the latest Video RAM work?
    >>>
    >>
    >> 64Mx8 means the silicon die has 512 megabits of RAM. A parallel
    >> bus of 8 bits in width, is used to read and write the memory in
    >> the chip. So, logically speaking, think of the memory as an
    >> array 64 million locations deep and 8 bits wide.
    >>
    >> Inside a typical memory chip, memory is broken into four arrays.
    >> Each array is "rows" x "columns" wide. The four separate
    >> arrays of memory are "banks". So, from a terminology perspective,
    >> that leaves "ranks", to describe the two banks of memory on a
    >> double sided DIMM.
    >>
    >> The internal organization of a memory chip, is only important
    >> when trying to figure out how big a memory chip that a
    >> Northbridge can support. Northbridges (or the integrated memory
    >> controller in an Athlon64/Opteron) have a limited number of
    >> address bits, to drive multiplexed row and column addresses to
    >> the memory chips. And, that is where the "density issue" comes
    >> in - when you can only see half the memory on a DIMM, it
    >> can be caused by a shortage of address bit from the memory
    >> controller interface.
    >>
    >> As for describing memory, a description of (16) 64Mx8 would be
    >> enough info to conclude a DIMM was double sided (two ranks). For
    >> reasons unknown to me, vendors refuse to describe it that way.
    >> After all, it is in their best interests, to provide as little
    >> info as possible about the shortcomings of any product.
    >>
    >> This will answer all your questions about GDDR3. One of the
    >> advantages of GDDR3, is reduced power consumption, due to
    >> the modified I/O used, and that is one of the reasons to look
    >> for it on a video card:
    >>
    >> http://download.micron.com/pdf/pubs/designline/dl402.pdf
    >>
    >> Paul
    >
    >I think I understand, maybe. I took digital electronics in tech school,
    >but didn't study RAM, didn't go that far, due to what they were training
    >us.
    >
    >So what you mean is that there are 64 million transistors and the buss that
    >transferrs the data to and from them is 8 bit across? So why is it that it
    >so happens that 64 times 8 comes out to 512? Is that just a coincidence,
    >or are there 8 different sets of 64 million transistors?
    >
    >Is there a site or video that you like to use to explain all of this?
    >
    >I am feeling pretty dumb right now, because I thought that I used to know
    >how this works and I don't remember now.
    >
    >Also, do you happen to know how many layers deep these transistors go, and
    >is that part of the equation?
    >
    >Would this mean that 128Mx8 mean that it was a 1 gig module? And then, if
    >there was 64Mx4 it would be a 256Meg module? Would this second example use
    >four chips?


    Memory Basics (slide show with voice)
    http://www.corsairmicro.com/memory_basics/153707/index.html
  7. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    On Mon, 28 Mar 2005 20:02:36 GMT, in <alt.comp.periphs.mainboard.asus>,
    signmeuptoo <signmeuptoo_no_spam@earthlink.net> wrote:
    >
    > Paul, could you please explain to me the ##Mx## thing? I mean, for
    > instance, is a 64Mx8 mean there there is 8 chips of 64 Meg capacity?
    [snip]

    No.

    Those designations say *nothing* about the physical layout (i.e., number of
    chips) of a SIMM or DIMM. For all intents and purposes, they are purely
    logical descriptors. In the case you cited, it means either of two things,
    depending on the context:

    1. - In the context of memory chips themselves, "64Mx8" would indicate a total
    of 512Mbits of memory, arranged as eight "columns" (or "rows", if you prefer;
    but this is starting to get into terminology more properly used when
    discussing the inner workings of the RAM chips themselves -- refresh cycles,
    pre-fetch delays, etc. -- where the context is somewhat different), each
    64Mbits deep. The "end point" of each of these eight "columns" is brought out
    to one of the pins on the chip; so that is how much data can be accessed at
    any given moment. Which "row" of data is presented at any given moment is
    determined by the memory controller via the address bus (and by convention, if
    not absolute necessity, these are kept "in sync" for all of the chips which
    form the array). Hence, for a standard 168-pin DIMM, which by definition
    provides a 64-bit (or 72-bit, if an ECC/parity type) data bus, you'd need
    eight (or nine) of these chips

    2. - In the context of SIMMs/DIMMs, all of the memory on that SIMM/DIMM
    (regardless of how many chips it might sport) is arranged "in aggregate" as
    eight "columns" (again, or "rows") of 64Mbits each. (Side note: This
    particular example would be an extremely odd SIMM/DIMM indeed; AFAIK, the
    largest "x8" SIMMs topped out at 16MB -- and even those were rare -- and there
    were never any "x8" DIMMs. But this is beside the point, really.)

    The key thing to understand is that in both cases, the (much) smaller number
    represents the number of bits which are *simultaneously* available (on the
    data bus) to the memory controller. Which means that the other (much larger)
    dimension represents the length of those "columns". And this is where "single
    bank" vs. "double bank" (sometimes called "single-sided" and "double-sided",
    respectively; but this incorrectly implies that the physical placement of the
    chips on the PCB is necessarily significant) gets into the act...

    The memory controllers integrated onto the motherboards of PCs can be (and
    often are) significantly limited in terms of how "long" a "column" they can
    support (there are some arcane technical reasons for this; don't sweat it for
    now). That "512Mx8" example you mention is a rather long column, by
    not-so-long-ago standards; and a (still hypothetical, I think -- but I've not
    checked lately) 1024Mx8 chip would represent a column length supported only by
    some of the very latest chipsets. So in order to provide "bigger" DIMMs,
    memory manufacturers sometimes double up the arrangement, effectively putting
    two DIMMs together into a single physical device. To you, it *looks* like a
    single DIMM; but from the computer's (specifically, the memory controller's)
    point of view, it's really *two* DIMMs, each half the size of the whole.
    Where this *can* get you into trouble is, those memory controllers are (at
    least typically) also limited in terms of how many memory *banks* they will
    support. So putting in a single so-called "double-sided" DIMM eats up two
    "banks" of the controller's capacity. Depending on the mobo design, you can
    run out of memory controller "banks" before you run out of physical DIMM
    slots.

    Clear as mud?

    --

    Jay T. Blocksom
    --------------------------------
    Appropriate Technology, Inc.
    usenet02[at]appropriate-tech.net

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  8. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    On Tue, 29 Mar 2005 03:07:40 GMT, in <alt.comp.periphs.mainboard.asus>,
    signmeuptoo <signmeuptoo_no_spam@earthlink.net> wrote:
    >
    [snip]
    >
    > So what you mean is that there are 64 million transistors
    [snip]

    Not transistors. Basically, little capacitors.

    > ...and the buss that
    > transferrs the data to and from them is 8 bit across?
    [snip]

    Correct.

    > So why is it that it
    > so happens that 64 times 8 comes out to 512?
    [snip]

    Uhhh... Because arithmetic works that way?

    > Is that just a coincidence,
    > or are there 8 different sets of 64 million transistors?
    >
    [snip]

    It's not a coincidence. It's math.

    > I am feeling pretty dumb right now, because I thought that I used to know
    > how this works and I don't remember now.
    >
    [snip]

    I suspect that part of the problem is that you are confusing yourself via
    "information overload" -- possibly exacerbated by some incorrect preconceived
    notions.

    > Also, do you happen to know how many layers deep these transistors go, and
    > is that part of the equation?
    >
    [snip]

    "Layers", per se, aren't really significant. You would do well to stop
    worrying about the *physical* construction of the memory chips and such, and
    concentrate on their logical attributes. In that sense, the "arrangement" of
    any given memory chip can be usefully thought of as a big (and usually very
    lopsided) two-dimensional array.

    > Would this mean that 128Mx8 mean that it was a 1 gig module?
    [snip]

    First, *IF* that term was being used in the context of a memory "module"
    (i.e., a DIMM or SIMM), then it would indeed indicate the capacity of that
    "module". But more typically, that term would be used to describe a memory
    *chip*.

    Second, your math is near-certainly off (at least the "x8" part nearly always
    denotes *bits*, not bytes). Hence, that would be a 128MByte chip.

    > And then, if
    > there was 64Mx4 it would be a 256Meg module?
    [snip]

    Again, this depends (almost purely) on the context; and the provisos regarding
    your math still apply. In this case, the most likely interpretation is a
    32MByte chip (four "columns" of 64Mbits each).

    > Would this second example use four chips?

    You mean if we were talking about a SIMM or DIMM? Then... maybe, or maybe
    not. But be aware that, AFAIK, there has never been any such thing as a
    "64Mx4" SIMM or DIMM (at least none that are applicable to anything resembling
    a PC). Bottom Line: The number of physical chips does not necessarily have
    *anything* to do with the "logical arrangement" (or capacity, or much of
    anything else) of any given SIMM or DIMM.

    See my other f'up to you for more of the gory details.

    --

    Jay T. Blocksom
    --------------------------------
    Appropriate Technology, Inc.
    usenet02[at]appropriate-tech.net

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  9. Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

    In article <53fsjrndd3l5.izr8xl4uhcih.dlg@40tude.net>,
    signmeuptoo@earthlink.net wrote:

    >
    > I think I understand, maybe. I took digital electronics in tech school,
    > but didn't study RAM, didn't go that far, due to what they were training
    > us.
    >
    > So what you mean is that there are 64 million transistors and the buss that
    > transferrs the data to and from them is 8 bit across? So why is it that it
    > so happens that 64 times 8 comes out to 512? Is that just a coincidence,
    > or are there 8 different sets of 64 million transistors?
    >
    > Is there a site or video that you like to use to explain all of this?
    >
    > I am feeling pretty dumb right now, because I thought that I used to know
    > how this works and I don't remember now.
    >
    > Also, do you happen to know how many layers deep these transistors go, and
    > is that part of the equation?
    >
    > Would this mean that 128Mx8 mean that it was a 1 gig module? And then, if
    > there was 64Mx4 it would be a 256Meg module? Would this second example use
    > four chips?

    I think the URL that Ed gave, is a good introduction. The only
    improvement I can see in this presentation, is if they dropped
    the cheesy voice over. I find it takes too long to skim through
    the info in the presentation. You'll have to be patient to
    listen to all of this:

    http://www.corsairmicro.com/memory_basics/153707/index.html

    It is easy to get the "eights" in all the math mixed up -
    I've even found errors counting bits and bytes on the web
    sites of the major memory manufacturers.

    The reason we are concerned with the internal arrangement of
    the memory chips, is to determine whether a Northbridge
    can interface correctly to them or not. The number of
    bits needed to address a row and a column inside the memory
    chip is important when figuring out whether a new denser
    memory chip will work with an old Northbridge.

    Page 16 of the Corsair presentation shows a picure. It
    shows four "slabs" made from 4096x1024x8 bits. That is
    a total of 4 megabytes in a slab. The four slabs or banks
    means the total memory for the memory chip is 16 megabytes.
    Now, all the memory is sitting flat on the chip, as seen
    in this presentation (this picture is for a different
    capacity of chip).

    http://www.lostcircuits.com/memory/eddr/2.shtml

    If you view the chip as a black box, it is a rectangle
    16 million locations on one edge and 8 bits wide on the
    other edge. I view the memory that way, because the
    memory is a "by 8" or "x8" device, and as you saw with
    each slab, every operation there involves a certain
    memory address and the 8 bits that reside there. If
    the chip was a x16, then each read or write to a location
    in one of the slabs, would change the 16 bits stored at
    that address.

    Now that we know the total capacity of the device
    (by multiplying rows * columns * bits_per_address * banks
    and dividing by eight_bits_per_byte to get bytes), we
    can count the memory chips on the DIMM and work out the
    capacity of the DIMM. If we had (16) 16mx8 chips, that
    is a total of 256 megabytes of memory.

    I think the Corsair slides make this easier to understand.
    USENET doesn't offer a chance to do good diagrams, and
    the Corsair slides give you something to look at.

    As for how the memory is constructed internally, I haven't
    a clue how they do it any more. That lostcircuits article
    gives some ideas.

    Paul
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