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More info?)
In article <Dqp2e.544$EE2.436@newsread2.news.pas.earthlink.net>, "H.W.
Stockman" <stockman3@earth-REMOVE_THIS-llink.net> wrote:
> "Ben Pope" <benpope81@_REMOVE_gmail.com> wrote in message
> news:1112135816.1468a1a8707a324ec1de245ef24e643b@teranews...
> > Stephen wrote:
> > > On Sun, 27 Mar 2005 23:55:41 +0100, Ben Pope
> > > <benpope81@_REMOVE_gmail.com> had a flock of green cheek conures
> > > squawk out:
> [...]
> > The voltage potential causes a current to flow. That current flows
> > through "thin wires". The "thin wires" have a high resistance. That
> > high resistance causes the "thin wires" to heat. The heat damages the
> > "thin wires".
> >
> > So my point was that heat damages CPUs, not voltage. The voltage causes
> > a current, which causes the heat, but the voltage itself didn't cause
> > the damage, the heat did. If the source is current limited, you could
> > apply a high voltage and not damage the chip.
>
> Metal melts do happen, but junction breakdown and oxide failure are possibly
> more important with ESD. Might a really high voltage cause migration across
> the n and p layers, making the semiconductor diodes non-functional, without
> melting?
>
> There may be some difference between the operative mechanism for damage from
> the 1000 to 40,000 volts one may produce walking across the carpet
> (dissipated in a millisecond), and damage from supplying an extra 0.5 volts
> (over months). Long-term damage occurs at well below the melting points of
> many of the metals in semiconductors (though perhaps not below the
> temperatures for fast mixing of oxide-metal "alloys"). Latent and/or
> long-term failures are probably by very different mechanisms than those that
> are caused by ESD.
And the mechanism in electromigration, is spelled out in its name.
There is actual material transport, so as time passes, the composition
of the "wires" in the IC changes. If a wire becomes thinner, the
propagation delay of a signal on the wire becomes longer. That
represents a timing change, and might be compensated for by turning
down the clock frequency in the affected part of the circuit.
In the semiconductor fab, great care is taken in choosing the
dimensions and composition of the "wires". If the circuit operates
at 3GHz, someone will try to make sure the wires are good to 3.5 or
4GHz. Since the wire dimensions affect the outside dimensions of
the silicon die, and the manufacturing economics, there are
incentives not to overdo it. From an overclockers perspective,
it means if you put some effort into your overclock, you could
enter the realm of accelerated life testing.
My info is years old, and was from a conversation with someone
at our fab (the head of the cell library development department).
Since materials and methods have changed a lot since
then, the design rules and margins used could be very different.
My info is only intended to illustrate a failure mechanism
which is different from the breakdown phenomenon the other
posters have mentioned.
There is a fine article here, full of wizzy words:
http://en.wikipedia.org/wiki/Electromigration
With regard to breakdown, there was one ISSCC paper presented by
Motorola, where the breakdown voltage was only listed as 0.2V
greater than absolute max for Vcore. Again, many overclockers will
choose to ignore Vcore_max, and it is anyone's guess as to when
they will be hit. Since there are devices like the OCZ DIMM
booster, and the DFI board that can run RAM at 4 volts, I guess
all this knowledge about absolute max is irrelevant
))
Presented by someone with only a casual interest in the subject,
Paul
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