A8N SLI Deluxe does not support ECC

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Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

Hi all,

I would like to share with everyone here a support question I left with
ASUS. If you like ECC as I do, this might be of interest to you.
I have not yet gotten any answer, just left the question there.
Do you think ASUS has stopped supporting ECC completely in the past
years, or if they just cannot get it right? Does anyone know if there
are any Socket 939 boards there with ECC really supported and working?
----------------------------

*CPU Vendor : AMD
*CPU Type : Athlon64 Venice 3500+
*CPU Speed : 2.2GHz
*Motherboard Revision : 1.02
*Motherboard BIOS Revision : 1011
*Memory Vendor : Kingston
*Memory Model : KVR400X72C3A/1G
*Memory Capacity : 2GB

Even though the A8N Deluxe bios (I have tried 1008 and 1011) does
include ECC setting, the integrated northbridge in Athlon64 is not
initialized correctly. PCI register 00:18.2 90 has "DIMM ECC Enable"
set, as well as 00:18.3 40 has ECC error reporting set, but those alone
do not enable ECC. The PCI registers 00:18.3 44 bits "Chip-Kill ECC Mode
Enable" and "ECC Enable" and 00:18.3 58 Scrub Control needs to be set also!

Have I missed something in BIOS settings, or are these settings really
missing? Where or when can I get a BIOS that fixes this issue?

To verify which registers are set and which not, I wrote a linux script:
http://hyvatti.iki.fi/~jaakko/sw/ecc.pl
Run that as root and look for 'ECC' and 'Scrub' in the output.

Jaakko Hyvätti

 

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Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

Jaakko Hyvätti wrote:

> Hi all,
>
> I would like to share with everyone here a support question I left with
> ASUS. If you like ECC as I do, this might be of interest to you.
> I have not yet gotten any answer, just left the question there.
> Do you think ASUS has stopped supporting ECC completely in the past
> years, or if they just cannot get it right? Does anyone know if there
> are any Socket 939 boards there with ECC really supported and working?
> ----------------------------
>
> *CPU Vendor : AMD
> *CPU Type : Athlon64 Venice 3500+
> *CPU Speed : 2.2GHz
> *Motherboard Revision : 1.02
> *Motherboard BIOS Revision : 1011
> *Memory Vendor : Kingston
> *Memory Model : KVR400X72C3A/1G
> *Memory Capacity : 2GB
>
> Even though the A8N Deluxe bios (I have tried 1008 and 1011) does
> include ECC setting, the integrated northbridge in Athlon64 is not
> initialized correctly. PCI register 00:18.2 90 has "DIMM ECC Enable"
> set, as well as 00:18.3 40 has ECC error reporting set, but those alone
> do not enable ECC. The PCI registers 00:18.3 44 bits "Chip-Kill ECC Mode
> Enable" and "ECC Enable" and 00:18.3 58 Scrub Control needs to be set also!
>
> Have I missed something in BIOS settings, or are these settings really
> missing? Where or when can I get a BIOS that fixes this issue?
>
> To verify which registers are set and which not, I wrote a linux script:
> http://hyvatti.iki.fi/~jaakko/sw/ecc.pl
> Run that as root and look for 'ECC' and 'Scrub' in the output.
>
> Jaakko Hyvätti
The memory controller is on the CPU, so the CPU has to support ECC. I
think only the Opterons support ECC. I think to use ECC you have to
build an Opteron Workstation. I think it has been rumored that AMD will
be coming out with a new socket that supports both the Opteron and
Athlon64 for the new Multicore chips. I will believe it when I see it.
Maybe if they do, then the cores will have the same memory controller,
or both will support ECC.

I might be wrong and maybe the Athlon64 does support ECC, I am not
really certain.

 

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Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

Last Boy Scout wrote:
> The memory controller is on the CPU, so the CPU has to support ECC. I
> think only the Opterons support ECC. I think to use ECC you have to
> build an Opteron Workstation. I think it has been rumored that AMD will
> be coming out with a new socket that supports both the Opteron and
> Athlon64 for the new Multicore chips. I will believe it when I see it.
> Maybe if they do, then the cores will have the same memory controller,
> or both will support ECC.

The values I describe in my message are read from the cpu north bridge
registers, they are available as pci registers. Below are the relevant
parts read out from the cpu that show that the cpu says it supports ECC
and the settings BIOS makes are just incorrect.

From the output of http://hyvatti.iki.fi/~jaakko/sw/ecc.pl on Athlon64
Venice 3500+ 2.2GHz:

....
00:18.2 90.L: 0x38078E00
....
Unbuffered DIMMs (14,1): 1
DIMM ECC Enable (15,1): 1
128-Bit/64-Bit (16,1): 1
....
00:18.3 40.L: 0x00003BFF
MCA Northbridge Control
....
Uncorrectable ECC Error Reporting Enable (31,1): 1
Correctable ECC Error Reporting Enable (32,1): 1
....
00:18.3 44.L: 0x00000040
MCA Northbridge Configuration
....
Chip-Kill ECC Mode Enable (9,1): 0
ECC Enable (10,1): 0
....
CPU ECC Error Log Enable (32,1): 0
00:18.3 48.L: 0x00000000
MCA Northbridge Status Low
Syndrome Bits 15­8 for Chip Kill ECC Mode (8,8): 0
Extended Error Code (16,4): 0
Error Code (32,16): 0
00:18.3 4C.L: 0x00000000
MCA Northbridge Status High
....
Syndrome Bits (7­0) for ECC Errors (17,8): 0
Correctable ECC Error (18,1): 0
Uncorrectable ECC Error (19,1): 0
Error Found by DRAM Scrubber (24,1): 0
....
00:18.3 58.L: 0x00000000
Scrub Control
Data Cache Scrub Rate (16,5): 0
L2 Cache Scrub Rate (24,5): 0
DRAM Scrub Rate (32,5): 0
00:18.3 5C.L: 0x86AE1CC0
DRAM Scrub Address Low (31,31): 1129778784 0x43570E60
DRAM Scrubber Redirect Enable (32,1): 0
00:18.3 60.L: 0x00000013
DRAM Scrub Address High (32,32): 19 0x13
....
0:18.3 E8.L: 0x00000519
Northbridge Capabilities
Memory Controller Capable (24,1): 1
Maximum DRAM Frequency (27,2): No limit
Chip-Kill ECC Capable (28,1): 1
ECC Capable (29,1): 1
Big MP Capable (30,1): 0
MP Capable (31,1): 0
128-Bit DRAM Capable (32,1): 1


--
Jaakko

 

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Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

Jaakko Hyvätti wrote:

Hi Jaakko!

> Even though the A8N Deluxe bios (I have tried 1008 and 1011) does
> include ECC setting, the integrated northbridge in Athlon64 is not
> initialized correctly. PCI register 00:18.2 90 has "DIMM ECC Enable"
> set, as well as 00:18.3 40 has ECC error reporting set, but those alone
> do not enable ECC. The PCI registers 00:18.3 44 bits "Chip-Kill ECC Mode
> Enable" and "ECC Enable" and 00:18.3 58 Scrub Control needs to be set also!

I am not sure about "ECC enable" (at least this register sounds like
being necessary for enabling ECC ;-)), but Chip-Kill (IMHO you need
special DIMMs for that, ECC-only-DIMMs are not sufficient!) and
scrubbing are IMHO not mandatory for correct ECC function.
You may check ECC function with memtest86+, this memory testing tool
reports if ECC is enabled and if it works correctly.

> Have I missed something in BIOS settings, or are these settings really
> missing? Where or when can I get a BIOS that fixes this issue?

The A8V mobos seem to have more ECC options in their BIOS (including
scrubbing and Chip-Kill), check the manuals on the Asus website.

> To verify which registers are set and which not, I wrote a linux script:
> http://hyvatti.iki.fi/~jaakko/sw/ecc.pl
> Run that as root and look for 'ECC' and 'Scrub' in the output.

Thanks for that script!

Christian

 

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Archived from groups: alt.comp.periphs.mainboard.asus (More info?)

Christian Busch wrote:
> I am not sure about "ECC enable" (at least this register sounds like
> being necessary for enabling ECC ;-)), but Chip-Kill (IMHO you need
> special DIMMs for that, ECC-only-DIMMs are not sufficient!) and
> scrubbing are IMHO not mandatory for correct ECC function.
> You may check ECC function with memtest86+, this memory testing tool
> reports if ECC is enabled and if it works correctly.

memtest86+ confirms that ECC is disabled. Thanks for reminding me about
this tool, I did not remember it reported ECC too. Chip-Kill really is
not necessary, but it would be foolish not to use hardware Scrubbing
when the memory system supports it! After all, what good is error
correction if the errors do not get corrected (back to the memory). I
know - they get corrected on memory read, but without scrubbing they may
accumulate and turn into uncorrectable multi bit errors.

Jaakko