Tiger MPX S2466 Chipset Question

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The AMD-768 southbridge connects to the AMD-762 northbridge via a
66MHz/32-bit PCI-X bus that shares with the two PCI-X slots, right? If I
plug a 33MHz extension card in one of those slots the whole bus will
fall back to 33MHz - *including* the interconnection of south to
northbridge (and thus the peripheral bandwith is limited to 133MB/s and
shared with both PCI-X slots)?!

Cheers,
Niko
 
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Am 20.09.2004 19:12 schrieb Nikolaus Riehm:
> plug a 33MHz extension card in one of those slots the whole bus will
> fall back to 33MHz - *including* the interconnection of south to
> northbridge (and thus the peripheral bandwith is limited to 133MB/s

ERR - Ok, it's only half the frequency but still 64-bit. But the
fallback takes place or am I wrong?

Niko
 
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"Nikolaus Riehm" <nikolaus.riehm@web.de> wrote in message
news:2r8n71F17kvo4U1@uni-berlin.de...
> Am 20.09.2004 19:12 schrieb Nikolaus Riehm:
> > plug a 33MHz extension card in one of those slots the whole bus will
> > fall back to 33MHz - *including* the interconnection of south to
> > northbridge (and thus the peripheral bandwith is limited to 133MB/s
>
> ERR - Ok, it's only half the frequency but still 64-bit. But the
> fallback takes place or am I wrong?
>
> Niko

you're right - if a 33Mhz card is plugged into a 66Mhz slot both 66Mhz slots
will be forced to 33Mhz. On the bright side it will still be a seperate bus
to the other 4 PCI slots.

Michael S.
 
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Am 20.09.2004 23:26 schrieb Nerds R Us (Poath Junction):
> "Nikolaus Riehm" <nikolaus.riehm@web.de> wrote in message
> news:2r8n71F17kvo4U1@uni-berlin.de...
>> Am 20.09.2004 19:12 schrieb Nikolaus Riehm:
>> > plug a 33MHz extension card in one of those slots the whole bus will
>> > fall back to 33MHz - *including* the interconnection of south to
>> > northbridge (and thus the peripheral bandwith is limited
>
> you're right - if a 33Mhz card is plugged into a 66Mhz slot both 66Mhz slots
> will be forced to 33Mhz. On the bright side it will still be a seperate bus
> to the other 4 PCI slots.

But that's the point: the southbridge is attached to the same PCI-X bus
and if this bus is bandwith limited due to a 33MHz PCI card the whole
bus scales down and henceforth the PCI host interface of the
southbridge, too. Or missed I something?

Niko
 
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"Nikolaus Riehm" <nikolaus.riehm@web.de> wrote in message
news:2r96h8F17hh9oU1@uni-berlin.de...
> Am 20.09.2004 23:26 schrieb Nerds R Us (Poath Junction):
> > "Nikolaus Riehm" <nikolaus.riehm@web.de> wrote in message
> > news:2r8n71F17kvo4U1@uni-berlin.de...
> >> Am 20.09.2004 19:12 schrieb Nikolaus Riehm:
> >> > plug a 33MHz extension card in one of those slots the whole bus will
> >> > fall back to 33MHz - *including* the interconnection of south to
> >> > northbridge (and thus the peripheral bandwith is limited
> >
> > you're right - if a 33Mhz card is plugged into a 66Mhz slot both 66Mhz
slots
> > will be forced to 33Mhz. On the bright side it will still be a seperate
bus
> > to the other 4 PCI slots.
>
> But that's the point: the southbridge is attached to the same PCI-X bus
> and if this bus is bandwith limited due to a 33MHz PCI card the whole
> bus scales down and henceforth the PCI host interface of the
> southbridge, too. Or missed I something?
>
> Niko

<http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505^809
^4886^4366,00.html> has the diagrams to explain it all. Well sorts of
explain it all.... The connection between the North and South bridge is
66Mhz and will always remain so. The PCI bus that connects directly to that
bus is normally 64bit 66mhz however it can fall back to 33Mhz if required
and the interface between that PCI and the north/south bridge will do the
conversion between 33mhz and 66 mhz for that connection. The 66mhz PCI could
have been integrated into the southbridge but the whole point is this method
allows 2 devices on the southbridge to use all their available bandwidth
talking to each other (eg a PCI card talking to the IDE controller) while
the 66mhz PCI can still get full use of the bus to talk to the northbridge.

Michael S.