Semprons ?

[Fish]

Archived from groups: alt.comp.hardware.overclocking.amd (More info?)

why do some Semprons claim to have a 256k 'exclusive' cache and others
don't?

 

[Guest]

Archived from groups: alt.comp.hardware.overclocking.amd (More info?)

On Sun, 05 Dec 2004 21:38:51 -0500, fish wrote:

> why do some Semprons claim to have a 256k 'exclusive' cache and others
> don't?

As long as I've been working with CPU's I've yet to hear or see any of
them make a claim. And I think I've already posted the answer from the
data sheets to you.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.htm

 

[Guest]

Archived from groups: alt.comp.hardware.overclocking.amd (More info?)

Thus spake fish:

>why do some Semprons claim to have a 256k 'exclusive' cache and others
>don't?

The chips are speaking to you? eek!

All Athlons have an exclusive cache architecture. Meaning that
information cached in L1 can not be in the L2 cache as well (it's
excluded, no duplications allowed). It saves space in the cache, but
is harder to implement.

Contrast with the P4's inclusive cache: a copy of the entire contents
of the L1 cache information is also held in L2 cache. Some of the L2
cache is wasted, but the cache structure can be clocked higher (which
was intel's goal).

--
sls

 

[Guest]

Archived from groups: alt.comp.hardware.overclocking.amd (More info?)

Awesome answer!!! Bet a lot of people picked up a new tidbit of info. Gotta
luv shared knowledge.

Garry.

"Satan's Little Sister" <littlesisterNO@SPAMsofthome.net> wrote in message
news:u358r0t2m6p243dn44h6jrekma07h9vmsl@4ax.com...
> Thus spake fish:
>
>>why do some Semprons claim to have a 256k 'exclusive' cache and others
>>don't?
>
> The chips are speaking to you? eek!
>
> All Athlons have an exclusive cache architecture. Meaning that
> information cached in L1 can not be in the L2 cache as well (it's
> excluded, no duplications allowed). It saves space in the cache, but
> is harder to implement.
>
> Contrast with the P4's inclusive cache: a copy of the entire contents
> of the L1 cache information is also held in L2 cache. Some of the L2
> cache is wasted, but the cache structure can be clocked higher (which
> was intel's goal).
>
> --
> sls