Maximum System Bus Speed

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What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
GA-7N400 Pro2 by the way
 
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Ziferten wrote:

> What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
> GA-7N400 Pro2 by the way
>
>

It's a 333MHz FSB processor.
 
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No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is just
AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
they multiply the real bus speed by 4x.

The maximum that the processor will run at depends on many things. If it's
un-locked you would be able to lower the multiplier and run it on a 200MHz
FSB, however if its one of the more recent locked models the maximum FSB
would be in the region of 175-190MHz, depending on how overclockable the cpu
is, how good your cooling is etc.

--
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"David Maynard" <dNOTmayn@ev1.net> wrote in message
news:1079lpdb7n97p69@corp.supernews.com...
> Ziferten wrote:
>
> > What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
> > GA-7N400 Pro2 by the way
> >
> >
>
> It's a 333MHz FSB processor.
>
 
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BigBadger wrote:

> No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is just
> AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
> they multiply the real bus speed by 4x.

Double and quad pumping the bus is not "hype." It's an engineering
technique for transferring data twice, or 4 times for quad, per clock cycle.

333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant number
from a performance standpoint.


> The maximum that the processor will run at depends on many things. If it's
> un-locked you would be able to lower the multiplier and run it on a 200MHz
> FSB, however if its one of the more recent locked models the maximum FSB
> would be in the region of 175-190MHz, depending on how overclockable the cpu
> is, how good your cooling is etc.
>

He didn't ask what speed he might be able to push it to. He asked "What is
the maximum that the Athlon XP 2800+ supports?" and the "Maximum System Bus
Speed" that the processor "supports" is the bus speed it's rated for.
 
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"Ziferten" wrote
> What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
> GA-7N400 Pro2 by the way


Hi,

the standard *system bus* for the XP2800+ is 333MHz, but you should be able
to run it on the 400MHz *system-bus*. This would depend on whether or not
your CPU was locked.

I'm not familiar with your mobo.
--
Wayne ][
 
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David Maynard wrote:
> BigBadger wrote:
>
>> No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is
>> just
>> AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
>> they multiply the real bus speed by 4x.
>
>
> Double and quad pumping the bus is not "hype." It's an engineering
> technique for transferring data twice, or 4 times for quad, per clock
> cycle.
>
> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant number
> from a performance standpoint.

I don't see much point in arguing this one in technical terms.

The fact is the term 'FSB' was used for many years to refer to the
memory/processor bus *clock frequency*, and reusing the same term for
the bus *bit rate* has caused no end of confusion and was therefore a
Bad Idea (tm).

One could also argue that use of the term 'hertz' (as in MHz) in
reference to anything other than the periodic interval of a waveform is
incorrect. Heinrich Rudolf is probably spinning in his grave :)

Intel themselves can't even get it straight: If you look up P3
processors at processorfinder.intel.com, 'Bus Speed' x 'Bus/Core Ratio'
= 'Processor Frequency', but the same calculation yields a number 4x
bigger than it should be when you look up 'pumped' processors.

>> The maximum that the processor will run at depends on many things. If
>> it's
>> un-locked you would be able to lower the multiplier and run it on a
>> 200MHz
>> FSB, however if its one of the more recent locked models the maximum FSB
>> would be in the region of 175-190MHz, depending on how overclockable
>> the cpu
>> is, how good your cooling is etc.
>>
>
> He didn't ask what speed he might be able to push it to. He asked "What
> is the maximum that the Athlon XP 2800+ supports?" and the "Maximum
> System Bus Speed" that the processor "supports" is the bus speed it's
> rated for.
>
 
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P2B wrote:

>
>
> David Maynard wrote:
>
>> BigBadger wrote:
>>
>>> No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is
>>> just
>>> AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
>>> they multiply the real bus speed by 4x.
>>
>>
>>
>> Double and quad pumping the bus is not "hype." It's an engineering
>> technique for transferring data twice, or 4 times for quad, per clock
>> cycle.
>>
>> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>> number from a performance standpoint.
>
>
> I don't see much point in arguing this one in technical terms.
>
> The fact is the term 'FSB' was used for many years to refer to the
> memory/processor bus *clock frequency*,

The term "FSB" has always referred to the "Front Side Bus" and not a
'clock'. What you refer to is simply that, for a considerable length of
time, the Front Side Bus 'speed', I.E. data rate, was coincident with the
base rate of the system clock.

It isn't, however, when the bus is dual or quad pumped.


> and reusing the same term for
> the bus *bit rate* has caused no end of confusion and was therefore a
> Bad Idea (tm).

I'm not using the term "FSB" to refer to a 'clock' or 'bit rate' or
anything other than what it's always referred to: the "Front Side Bus."


> One could also argue that use of the term 'hertz' (as in MHz) in
> reference to anything other than the periodic interval of a waveform is
> incorrect. Heinrich Rudolf is probably spinning in his grave :)

Yes. In previous discussions I've also pointed out that same argument as
the perspective of the 'purist'. It does, however, beg the question about
the data rate of a 166.6Mhz clocked double data rate bus being 333 'what'?
To which I mused perhaps we should regret having changed from the original
designation of "Cycles/Second" to "Hertz." (It's interesting to note that
few would find such a problem with a bus rate designation of 333
'Mega-Cycles/Second' but do when the synonym "Hertz" is substituted)

"MHz" may not be a 'purist' form of usage here but it captures the
pertinent aspect of the bus speed in a context consistent with the single
data rate bus and is certainly not 'hype', which was the original point.

I.E. Of what relevance to the 'real' (sic) 'bus speed' is it how the
designer derived his timing signals? Other than to 'techies', that is.
 
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~misfit~ wrote:

> David Maynard wrote:
>
>>BigBadger wrote:
>>
>>
>>>No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>>>is just AMD hype to sell the virtues of the DDR bus. Intel do the
>>>same trick but they multiply the real bus speed by 4x.
>>
>>Double and quad pumping the bus is not "hype." It's an engineering
>>technique for transferring data twice, or 4 times for quad, per clock
>>cycle.
>>
>>333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>number from a performance standpoint.
>
>
> Yes, but David my friend, you said "333MHz FSB". That is plainly incorrect,
> the "MHz" part of it.

Feel free to explain 333 'what' it is ;)
 
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David Maynard wrote:
> BigBadger wrote:
>
>> No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>> is just AMD hype to sell the virtues of the DDR bus. Intel do the
>> same trick but they multiply the real bus speed by 4x.
>
> Double and quad pumping the bus is not "hype." It's an engineering
> technique for transferring data twice, or 4 times for quad, per clock
> cycle.
>
> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
> number from a performance standpoint.

Oh dear, oh dear, here we go again ... :) It depends on whether you measure
the control lines or the data lines for quoting the "bus speed" number.

I actually think a more accurate way of representing it (performance-wise)
is a 128-bit bus (DDR) or 256-bit bus (QDR), both running at 166MHz. A good
example is the latency for main memory. Say you have a 166MHz DDR system
(aka DDR333), and a 100MHz QDR system (aka QDR400), and the CPU runs at 1GHz
(6.0x for DDR, 10.0x for QDR). Excluding memory latencies, to fill a
randomly-accessed 64-byte cache line would take:
Waiting for bus strobe: 3.0 cycles (DDR system), 5.0 cycles (QDR system)
Transferring data: 24 cycles (DDR), 20 cycles (QDR)
Total: 27 cycles (DDR), 25 cycles (QDR)
So DDR333 is, under random access conditions, only marginally slower than
QDR400. The actual break-even point is 180MHz (actually slightly above due
to memory latencies), but hopefully you get the idea. Of course, the QDR
system will perform better under "streaming" type conditions, where the
higher latency won't matter so much.

Incidentally, this issue is exasparated by the P4's 128-byte cache line, as
opposed to the 64-byte cache line of the K7.

Finally, using the non-multiplied speed would stop people complaining that
their motherboard only goes up to 250MHz :)

[...]

--
Michael Brown
www.emboss.co.nz : OOS/RSI software and more :)
Add michael@ to emboss.co.nz - My inbox is always open
 
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Michael Brown wrote:
> David Maynard wrote:
>
>>BigBadger wrote:
>>
>>
>>>No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>>>is just AMD hype to sell the virtues of the DDR bus. Intel do the
>>>same trick but they multiply the real bus speed by 4x.
>>
>>Double and quad pumping the bus is not "hype." It's an engineering
>>technique for transferring data twice, or 4 times for quad, per clock
>>cycle.
>>
>>333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>number from a performance standpoint.
>
>
> Oh dear, oh dear, here we go again ... :) It depends on whether you measure
> the control lines or the data lines for quoting the "bus speed" number.

No it doesn't. It has to do with how many data transfer cycles there are.

> I actually think a more accurate way of representing it (performance-wise)
> is a 128-bit bus (DDR) or 256-bit bus (QDR), both running at 166MHz.

Except it isn't '128 bits' or '256 bits' wide. It does, however, transfer
data at either 2, for dual pumped, or 4 times, for quad pumped, the system
clock rate.

> A good
> example is the latency for main memory.

Which is a separate component independent of the bus and not even ON, or
even necessarily run at the speed of, the bus at issue.

> Say you have a 166MHz DDR system
> (aka DDR333), and a 100MHz QDR system (aka QDR400), and the CPU runs at 1GHz
> (6.0x for DDR, 10.0x for QDR). Excluding memory latencies, to fill a
> randomly-accessed 64-byte cache line would take:
> Waiting for bus strobe: 3.0 cycles (DDR system), 5.0 cycles (QDR system)
> Transferring data: 24 cycles (DDR), 20 cycles (QDR)
> Total: 27 cycles (DDR), 25 cycles (QDR)
>
> So DDR333 is, under random access conditions, only marginally slower than
> QDR400. The actual break-even point is 180MHz (actually slightly above due
> to memory latencies), but hopefully you get the idea. Of course, the QDR
> system will perform better under "streaming" type conditions, where the
> higher latency won't matter so much.

No, you're analyzing the memory, not the processor bus.

We can sit here all day long proposing new terminology but that's
irrelevant to the matter.


> Incidentally, this issue is exasparated by the P4's 128-byte cache line, as
> opposed to the 64-byte cache line of the K7.

Processor (L2) cache has nothing to do with bus speed. It affects processor
performance, of course, but then so does the L1 cache, cpu architecture,
and core speed: none of which have anything to do with the bus speed either.

Btw, what don't you call a 3.4 Gig P4 a 200Mhz P4 because the 'real clock'
(sic) is 200 Mhz. That 3.4 Gig number is just 'hype'.

> Finally, using the non-multiplied speed would stop people complaining that
> their motherboard only goes up to 250MHz :)

Requiring everyone to use the same bus and speed would solve it too but
that hardly means it's desirable.

>
> [...]
>
> --
> Michael Brown
> www.emboss.co.nz : OOS/RSI software and more :)
> Add michael@ to emboss.co.nz - My inbox is always open
>
>
 
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A bus must follow the same speed limits as private automobiles; measured in
KPh or MPh (Kilo packets pre hour or Mega Packets per hour. So these
processor Front Side Buses are vastly exceeding legal limits, and should be
reined in. Likely pumping the accelerator too often is the cause.

--
Phil Weldon, pweldonatmindjumpdotcom
For communication,
replace "at" with the 'at sign'
replace "mindjump" with "mindspring."
replace "dot" with "."
 
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~misfit~ wrote:

> David Maynard wrote:
>
>>~misfit~ wrote:
>>
>>
>>>David Maynard wrote:
>>>
>>>
>>>>BigBadger wrote:
>>>>
>>>>
>>>>
>>>>>No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>>>>>is just AMD hype to sell the virtues of the DDR bus. Intel do the
>>>>>same trick but they multiply the real bus speed by 4x.
>>>>
>>>>Double and quad pumping the bus is not "hype." It's an engineering
>>>>technique for transferring data twice, or 4 times for quad, per
>>>>clock cycle.
>>>>
>>>>333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>>>number from a performance standpoint.
>>>
>>>
>>>Yes, but David my friend, you said "333MHz FSB". That is plainly
>>>incorrect, the "MHz" part of it.
>>
>>Feel free to explain 333 'what' it is ;)
>
>
> MegaSignals/second (MS/s). <g> Two signals per hertz.

Hehe. Sure. That'll clear it up.

I can just hear it now: people complaining it's (really) 'MicroSofts'/s ;)

Btw, Hertz is defined as "hertz (Hz): 1. The SI unit of frequency, equal to
one cycle per second. Note: A periodic phenomenon that has a period of one
second has a frequency of one hertz. (188) 2. A unit of frequency which is
equivalent to one cycle per second."

http://www.its.bldrdoc.gov/fs-1037/dir-018/_2563.htm

And the data transfer rate qualifies as "a periodic phenomenon."

"Frequency" is not just an electrical term and is not restricted to
electronic waveforms.

You have to be careful about sloppy definitions. For example, look at this
one: http://www.webopedia.com/TERM/H/Hz.html

"Short for Hertz, a unit of frequency of electrical vibrations equal to one
cycle per second. The Hertz is named after Heinrich Hertz, who first
detected electromagnetic waves."

Oh really? Only "electrical vibrations?" So Hertz doesn't apply to sound
waves? The range of human hearing isn't 20 Hz to 20,000 Hz?

Then we're going to have to send all our astrophysicists back to school too
because they think frequency applies to orbits.

http://arxiv.org/abs/astro-ph/0110209

"We compute the maximum orbital frequency of stable circular motion around
uniformly rotating strange stars described by the MIT bag model. The
calculations are performed for both normal and supramassive constant baryon
mass sequences of strange stars rotating at all possible rates. We find the
lower limits on the maximum orbital frequency and discuss them for a range
of masses and for all rotational frequencies allowed in the model
considered. We show that for slowly and moderately rotating strange stars
the maximum value of orbital frequency can be a good indicator of the mass
of the compact object. However, for rapidly rotating strange stars the same
value of orbital frequency in the innermost stable circular orbit is
obtained for stars with masses ranging from that of a planetoid to about
three solar masses. At sufficiently high rotation rates of the strange
star, the rotational period alone constrains the stellar mass to a
surprisingly narrow range."


That second definition falls into the trap I allude to with my lament of
the change from Cycles/s to Hertz: that using the name "Hertz" suddenly
limits the scope.
 
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Alright, so I didn't get an answer, but I learned way more about Hertz!
"Ziferten" <ehaag_0@hotmail.com> wrote in message
news:rV3dc.23273$YC5.20163@twister.rdc-kc.rr.com...
> What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
> GA-7N400 Pro2 by the way
>
>
 
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Ziferten wrote:
> Alright, so I didn't get an answer, but I learned way more about Hertz!

Hehe. Well, actually you did. What it "supports" is what it's rated at.

I rather suspect you want to know what you can 'get out of it' and that was
answered too.


> "Ziferten" <ehaag_0@hotmail.com> wrote in message
> news:rV3dc.23273$YC5.20163@twister.rdc-kc.rr.com...
>
>>What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
>>GA-7N400 Pro2 by the way
>>
>>
>
>
>
 
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You said 333MHz...a MHz is a measure of frequency. The frequency in MHz of a
XP2800+ FSB is 166...end of story.

--
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"David Maynard" <dNOTmayn@ev1.net> wrote in message
news:107a2lp7v48lta7@corp.supernews.com...
> BigBadger wrote:
>
> > No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is
just
> > AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
> > they multiply the real bus speed by 4x.
>
> Double and quad pumping the bus is not "hype." It's an engineering
> technique for transferring data twice, or 4 times for quad, per clock
cycle.
>
> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant number
> from a performance standpoint.
>
>
> > The maximum that the processor will run at depends on many things. If
it's
> > un-locked you would be able to lower the multiplier and run it on a
200MHz
> > FSB, however if its one of the more recent locked models the maximum FSB
> > would be in the region of 175-190MHz, depending on how overclockable the
cpu
> > is, how good your cooling is etc.
> >
>
> He didn't ask what speed he might be able to push it to. He asked "What is
> the maximum that the Athlon XP 2800+ supports?" and the "Maximum System
Bus
> Speed" that the processor "supports" is the bus speed it's rated for.
>
 
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BigBadger wrote:

> You said 333MHz...a MHz is a measure of frequency. The frequency in MHz of a
> XP2800+ FSB is 166...end of story.
>

Yes. Hertz is "a measure of frequency." It's your assumption that a 'clock'
is the only thing of interest that's the problem.

The bus data rate of an XP2800+ is 333Mhz because that is the frequency of
data arrival.
 
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kinda.... i was really after whether or not the 200(MHz? : )) bus was safe
for the processor
"David Maynard" <dNOTmayn@ev1.net> wrote in message
news:107e56l2817b35a@corp.supernews.com...
> Ziferten wrote:
> > Alright, so I didn't get an answer, but I learned way more about Hertz!
>
> Hehe. Well, actually you did. What it "supports" is what it's rated at.
>
> I rather suspect you want to know what you can 'get out of it' and that
was
> answered too.
>
>
> > "Ziferten" <ehaag_0@hotmail.com> wrote in message
> > news:rV3dc.23273$YC5.20163@twister.rdc-kc.rr.com...
> >
> >>What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
> >>GA-7N400 Pro2 by the way
> >>
> >>
> >
> >
> >
>
 
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>
> Yes. In previous discussions I've also pointed out that same argument as
> the perspective of the 'purist'. It does, however, beg the question about
> the data rate of a 166.6Mhz clocked double data rate bus being 333 'what'?
> To which I mused perhaps we should regret having changed from the original
> designation of "Cycles/Second" to "Hertz." (It's interesting to note that
> few would find such a problem with a bus rate designation of 333
> 'Mega-Cycles/Second' but do when the synonym "Hertz" is substituted)
>
Hertz is a measure of Mega Cycles per second...we both agree on that.
The dictionary 'physics' definition of a cycle is:
one complete oscillation: one complete continuous change in the magnitude of
an oscillating quantity or system that brings the system back to its
original energy state.
Therefore it does not matter how many data points is carried on the wave,
the frequency is the number of cycles (or oscillations) per second and for
an XP2800+ this is 166,600,000....or 166MHz
 
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BigBadger wrote:

>>Yes. In previous discussions I've also pointed out that same argument as
>>the perspective of the 'purist'. It does, however, beg the question about
>>the data rate of a 166.6Mhz clocked double data rate bus being 333 'what'?
>>To which I mused perhaps we should regret having changed from the original
>>designation of "Cycles/Second" to "Hertz." (It's interesting to note that
>>few would find such a problem with a bus rate designation of 333
>>'Mega-Cycles/Second' but do when the synonym "Hertz" is substituted)
>>
>
> Hertz is a measure of Mega Cycles per second...we both agree on that.

Yep. Now, cycles of what?

> The dictionary 'physics' definition of a cycle is:
> one complete oscillation: one complete continuous change in the magnitude of
> an oscillating quantity or system that brings the system back to its
> original energy state.
> Therefore it does not matter how many data points is carried on the wave,
> the frequency is the number of cycles (or oscillations) per second and for
> an XP2800+ this is 166,600,000....or 166MHz

Except that we aren't talking about the 'physics' of a waveform in this
context. We're talking about the bus data rate and that is 333Mhz.

Let me give an analogy. Do you care what the magnetic flux on the platters
in a 120 gig hard drive looks like? Do you care if it's FM encoded, or MFM
encoded, or RLL encoded? No, all you care about is that it stores 120 gig.
That is the 'relevant' summary information: the data you get.

The same applies to the bus. It is of technical interest that it's a
166.6MHZ clocked double data rate bus but the summary of interest is that
it transfers data at 333MHz.

Both representations are perfectly valid in the context of what they are
describing and neither is 'hype'.
 
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Ziferten wrote:

> kinda.... i was really after whether or not the 200(MHz? : )) bus was safe
> for the processor

A 200Mhz bus (in this case you mean the base clock rate) is 'safe' in that
it, alone, isn't going to physically damage the processor.

Whether it will run at that speed is a bit more problematic.

As an example, I have an AMD mobile, 512K cache (Barton), 2400+ running
2,400MHz on a 200MHz (base clock rate) bus although it's spec'd for a
133.3Mhz (base clock rate) bus. But I was able to run it like that because
it's multiplier is unlocked and it took overvolting the processor, memory,
and the chipset (probably because the memory is el-cheapo junk).


> "David Maynard" <dNOTmayn@ev1.net> wrote in message
> news:107e56l2817b35a@corp.supernews.com...
>
>>Ziferten wrote:
>>
>>>Alright, so I didn't get an answer, but I learned way more about Hertz!
>>
>>Hehe. Well, actually you did. What it "supports" is what it's rated at.
>>
>>I rather suspect you want to know what you can 'get out of it' and that
>
> was
>
>>answered too.
>>
>>
>>
>>>"Ziferten" <ehaag_0@hotmail.com> wrote in message
>>>news:rV3dc.23273$YC5.20163@twister.rdc-kc.rr.com...
>>>
>>>
>>>>What is the maximum that the Athlon XP 2800+ supports? I use a Gigabyte
>>>>GA-7N400 Pro2 by the way
>>>>
>>>>
>>>
>>>
>>>
>
>
 
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~misfit~ wrote:

> David Maynard wrote:
>
>>~misfit~ wrote:
>>
>>
>>>David Maynard wrote:
>>>
>>>
>>>>~misfit~ wrote:
>>>>
>>>>
>>>>
>>>>>David Maynard wrote:
>>>>>
>>>>>
>>>>>
>>>>>>BigBadger wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>>No it's not 333MHz, it's actually a 166 'MHz' FSB
>>>>>>>processor....333 is just AMD hype to sell the virtues of the DDR
>>>>>>>bus. Intel do the same trick but they multiply the real bus
>>>>>>>speed by 4x.
>>>>>>
>>>>>>Double and quad pumping the bus is not "hype." It's an engineering
>>>>>>technique for transferring data twice, or 4 times for quad, per
>>>>>>clock cycle.
>>>>>>
>>>>>>333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>>>>>number from a performance standpoint.
>>>>>
>>>>>
>>>>>Yes, but David my friend, you said "333MHz FSB". That is plainly
>>>>>incorrect, the "MHz" part of it.
>>>>
>>>>Feel free to explain 333 'what' it is ;)
>>>
>>>
>>>MegaSignals/second (MS/s). <g> Two signals per hertz.
>>
>>Hehe. Sure. That'll clear it up.
>>
>>I can just hear it now: people complaining it's (really)
>>'MicroSofts'/s ;)
>>
>>Btw, Hertz is defined as "hertz (Hz): 1. The SI unit of frequency,
>>equal to one cycle per second. Note: A periodic phenomenon that has a
>>period of one second has a frequency of one hertz. (188) 2. A unit of
>>frequency which is equivalent to one cycle per second."
>>
>>http://www.its.bldrdoc.gov/fs-1037/dir-018/_2563.htm
>>
>>And the data transfer rate qualifies as "a periodic phenomenon."
>>
>>"Frequency" is not just an electrical term and is not restricted to
>>electronic waveforms.
>>
>>You have to be careful about sloppy definitions. For example, look at
>>this one: http://www.webopedia.com/TERM/H/Hz.html
>>
>>"Short for Hertz, a unit of frequency of electrical vibrations equal
>>to one cycle per second. The Hertz is named after Heinrich Hertz, who
>>first detected electromagnetic waves."
>>
>>Oh really? Only "electrical vibrations?" So Hertz doesn't apply to
>>sound waves? The range of human hearing isn't 20 Hz to 20,000 Hz?
>>
>>Then we're going to have to send all our astrophysicists back to
>>school too because they think frequency applies to orbits.
>>
>>http://arxiv.org/abs/astro-ph/0110209
>>
>>"We compute the maximum orbital frequency of stable circular motion
>>around uniformly rotating strange stars described by the MIT bag
>>model. The calculations are performed for both normal and
>>supramassive constant baryon mass sequences of strange stars rotating
>>at all possible rates. We find the lower limits on the maximum
>>orbital frequency and discuss them for a range of masses and for all
>>rotational frequencies allowed in the model considered. We show that
>>for slowly and moderately rotating strange stars the maximum value of
>>orbital frequency can be a good indicator of the mass of the compact
>>object. However, for rapidly rotating strange stars the same value of
>>orbital frequency in the innermost stable circular orbit is obtained
>>for stars with masses ranging from that of a planetoid to about three
>>solar masses. At sufficiently high rotation rates of the strange
>>star, the rotational period alone constrains the stellar mass to a
>>surprisingly narrow range."
>>
>>
>>That second definition falls into the trap I allude to with my lament
>>of the change from Cycles/s to Hertz: that using the name "Hertz"
>>suddenly limits the scope.
>
>
> Yup, it's a mine-field. I just personally have an aversion to people talking
> about "800MHz" (FI) FSB's when it's really 200Mhz. Paint me pedantic.

When "it's" the base clock you're right. But when "it's" the data rate then
"it's" 'really' 800MHz.


> --
> ~misfit~
>
>
 
G

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Archived from groups: alt.comp.hardware.overclocking (More info?)

The data transfer occurs 800,000,000 times per second. There are
800,000,000 clocking edges per second, on each of which a transfer of the
full bus width occurs. Now, is it more meaningful to call that transfering
at a rate of 800,000,000 times per second or 200,000,000 X times 4 per
second? As for the clocks that controls the memory, they generate
400,000,000 pulses per second, and are derived from 800,000,000 pulses per
second (to get the offset.) The FSB transfers to and from memory at 800 MHz
for Pentium 4 CPU's rated for that. You can call it anything you want to,
but you may not be understood, and certainly you will not change reality.

--
Phil Weldon, pweldonatmindjumpdotcom
For communication,
replace "at" with the 'at sign'
replace "mindjump" with "mindspring."
replace "dot" with "."


"~misfit~" <misfit61nz@yahoomung.co.nz> wrote in message
news:AbHdc.10438$d%6.184741@news.xtra.co.nz...
> David Maynard wrote:
> > ~misfit~ wrote:
> >
> >> David Maynard wrote:
> >>
> >>> ~misfit~ wrote:
> >>>
> >>>
> >>>> David Maynard wrote:
> >>>>
> >>>>
> >>>>> BigBadger wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>>> No it's not 333MHz, it's actually a 166 'MHz' FSB
> >>>>>> processor....333 is just AMD hype to sell the virtues of the DDR
> >>>>>> bus. Intel do the same trick but they multiply the real bus
> >>>>>> speed by 4x.
> >>>>>
> >>>>> Double and quad pumping the bus is not "hype." It's an engineering
> >>>>> technique for transferring data twice, or 4 times for quad, per
> >>>>> clock cycle.
> >>>>>
> >>>>> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
> >>>>> number from a performance standpoint.
> >>>>
> >>>>
> >>>> Yes, but David my friend, you said "333MHz FSB". That is plainly
> >>>> incorrect, the "MHz" part of it.
> >>>
> >>> Feel free to explain 333 'what' it is ;)
> >>
> >>
> >> MegaSignals/second (MS/s). <g> Two signals per hertz.
> >
> > Hehe. Sure. That'll clear it up.
> >
> > I can just hear it now: people complaining it's (really)
> > 'MicroSofts'/s ;)
> >
> > Btw, Hertz is defined as "hertz (Hz): 1. The SI unit of frequency,
> > equal to one cycle per second. Note: A periodic phenomenon that has a
> > period of one second has a frequency of one hertz. (188) 2. A unit of
> > frequency which is equivalent to one cycle per second."
> >
> > http://www.its.bldrdoc.gov/fs-1037/dir-018/_2563.htm
> >
> > And the data transfer rate qualifies as "a periodic phenomenon."
> >
> > "Frequency" is not just an electrical term and is not restricted to
> > electronic waveforms.
> >
> > You have to be careful about sloppy definitions. For example, look at
> > this one: http://www.webopedia.com/TERM/H/Hz.html
> >
> > "Short for Hertz, a unit of frequency of electrical vibrations equal
> > to one cycle per second. The Hertz is named after Heinrich Hertz, who
> > first detected electromagnetic waves."
> >
> > Oh really? Only "electrical vibrations?" So Hertz doesn't apply to
> > sound waves? The range of human hearing isn't 20 Hz to 20,000 Hz?
> >
> > Then we're going to have to send all our astrophysicists back to
> > school too because they think frequency applies to orbits.
> >
> > http://arxiv.org/abs/astro-ph/0110209
> >
> > "We compute the maximum orbital frequency of stable circular motion
> > around uniformly rotating strange stars described by the MIT bag
> > model. The calculations are performed for both normal and
> > supramassive constant baryon mass sequences of strange stars rotating
> > at all possible rates. We find the lower limits on the maximum
> > orbital frequency and discuss them for a range of masses and for all
> > rotational frequencies allowed in the model considered. We show that
> > for slowly and moderately rotating strange stars the maximum value of
> > orbital frequency can be a good indicator of the mass of the compact
> > object. However, for rapidly rotating strange stars the same value of
> > orbital frequency in the innermost stable circular orbit is obtained
> > for stars with masses ranging from that of a planetoid to about three
> > solar masses. At sufficiently high rotation rates of the strange
> > star, the rotational period alone constrains the stellar mass to a
> > surprisingly narrow range."
> >
> >
> > That second definition falls into the trap I allude to with my lament
> > of the change from Cycles/s to Hertz: that using the name "Hertz"
> > suddenly limits the scope.
>
> Yup, it's a mine-field. I just personally have an aversion to people
talking
> about "800MHz" (FI) FSB's when it's really 200Mhz. Paint me pedantic.
> --
> ~misfit~
>
>
 
G

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Archived from groups: alt.comp.hardware.overclocking (More info?)

David Maynard wrote:
> Michael Brown wrote:
>> David Maynard wrote:
>>> BigBadger wrote:
>>>> No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>>>> is just AMD hype to sell the virtues of the DDR bus. Intel do the
>>>> same trick but they multiply the real bus speed by 4x.
>>>
>>> Double and quad pumping the bus is not "hype." It's an engineering
>>> technique for transferring data twice, or 4 times for quad, per
>>> clock cycle.
>>>
>>> 333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>> number from a performance standpoint.
>>
>> Oh dear, oh dear, here we go again ... :) It depends on whether you
>> measure the control lines or the data lines for quoting the "bus
>> speed" number.
>
> No it doesn't. It has to do with how many data transfer cycles there
> are.

This is exactly what I mean :) There are some lines on the bus that
"operate" at <x> MHz, and some that "operate" at <4*x> MHz. What, then, is
the bus speed? There are valid arguments for both directions. From a
performance standpoint, I personally think the <x> MHz number is better (and
expand the "bus width" accordingly); you obviously think the MHz should be
scaled.

>> I actually think a more accurate way of representing it
>> (performance-wise) is a 128-bit bus (DDR) or 256-bit bus (QDR), both
>> running at 166MHz.
>
> Except it isn't '128 bits' or '256 bits' wide. It does, however,
> transfer data at either 2, for dual pumped, or 4 times, for quad
> pumped, the system clock rate.

Hence why I explicitly said "performance-wise". The question I was answering
was:
Which closer represents the performance of a 64 bit <x> MHz QDR bus?
(a) A 64-bit <4*x> MHz SDR bus
(b) A 256-bit <x> MHz SDR bus
The correct answer is (b).

Of course, at the low level, it's still a 64-bit bus, except one part is
operating at <x> MHz and another part at <4*x> MHz.

[...]
>> Say you have a 166MHz DDR system
>> (aka DDR333), and a 100MHz QDR system (aka QDR400), and the CPU runs
>> at 1GHz (6.0x for DDR, 10.0x for QDR). Excluding memory latencies,
>> to fill a randomly-accessed 64-byte cache line would take:
>> Waiting for bus strobe: 3.0 cycles (DDR system), 5.0 cycles (QDR
>> system) Transferring data: 24 cycles (DDR), 20 cycles (QDR)
>> Total: 27 cycles (DDR), 25 cycles (QDR)
>>
>> So DDR333 is, under random access conditions, only marginally slower
>> than QDR400. The actual break-even point is 180MHz (actually
>> slightly above due to memory latencies), but hopefully you get the
>> idea. Of course, the QDR system will perform better under
>> "streaming" type conditions, where the higher latency won't matter
>> so much.
>
> No, you're analyzing the memory, not the processor bus.

Errm, not at all. I specifically EXCLUDE any memory performance
considerations from the analysis: see the third line of your quoted section.
I'm solely analysing how long it would take to fill (or write out) a
processor cache line over a DDR/QDR bus, which is pretty much all the
processor bus is used for. The exact same argument applies to the
point-to-point DDR busses in a K7 SMP system, if having memory in the
picture makes things confusing for you.

[...]
>> Incidentally, this issue is exasparated by the P4's 128-byte cache
>> line, as opposed to the 64-byte cache line of the K7.
>
> Processor (L2) cache has nothing to do with bus speed.

Hence my "incidentally" (spot the recurring theme here: I don't usually put
in words for no reason). The processor cache line size (note: cache LINE
size, not cache size or anything else) and bus performance characteristics
are quite interlinked for the performance of a processor. The larger cache
line size improves streaming performance and decreases random-access
performance, which is exactly the same characteristics as a QDR bus. My
point was that the P4 has been heavily tweaked towards streaming
computations, as opposed to having fast random-access times.

[...]
> Btw, what don't you call a 3.4 Gig P4 a 200Mhz P4 because the 'real
> clock' (sic) is 200 Mhz. That 3.4 Gig number is just 'hype'.

Why don't you call it a 6.8GHz P4? :p

I call it a 3.4GHz CPU because it operates on a 3.4GHz clock rate. The
external signalling is at 200MHz or 800MHz, but this has not the operating
frequency of the CPU itself. DDR/QDR is a much trickier problem, as part of
it is operating at 200MHz, and another part at 800MHz. Sort of as if the
ALUs all operated at 6.8GHz and the floating point units all operated at
3.4GHz. Oh, dearie me ...

[...]

--
Michael Brown
www.emboss.co.nz : OOS/RSI software and more :)
Add michael@ to emboss.co.nz - My inbox is always open
 
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Archived from groups: alt.comp.hardware.overclocking (More info?)

Michael Brown wrote:
> David Maynard wrote:
>
>>Michael Brown wrote:
>>
>>>David Maynard wrote:
>>>
>>>>BigBadger wrote:
>>>>
>>>>>No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
>>>>>is just AMD hype to sell the virtues of the DDR bus. Intel do the
>>>>>same trick but they multiply the real bus speed by 4x.
>>>>
>>>>Double and quad pumping the bus is not "hype." It's an engineering
>>>>technique for transferring data twice, or 4 times for quad, per
>>>>clock cycle.
>>>>
>>>>333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
>>>>number from a performance standpoint.
>>>
>>>Oh dear, oh dear, here we go again ... :) It depends on whether you
>>>measure the control lines or the data lines for quoting the "bus
>>>speed" number.
>>
>>No it doesn't. It has to do with how many data transfer cycles there
>>are.
>
>
> This is exactly what I mean :) There are some lines on the bus that
> "operate" at <x> MHz, and some that "operate" at <4*x> MHz.

It is irrelevant what "some lines" do. What's relevant is the data rate.


> What, then, is
> the bus speed?

The bus 'speed' is the data rate.

> There are valid arguments for both directions. From a
> performance standpoint, I personally think the <x> MHz number is better (and
> expand the "bus width" accordingly); you obviously think the MHz should be
> scaled.

It isn't a matter of 'scaling' anything. The data rate is the data rate.


>>>I actually think a more accurate way of representing it
>>>(performance-wise) is a 128-bit bus (DDR) or 256-bit bus (QDR), both
>>>running at 166MHz.
>>
>>Except it isn't '128 bits' or '256 bits' wide. It does, however,
>>transfer data at either 2, for dual pumped, or 4 times, for quad
>>pumped, the system clock rate.
>
>
> Hence why I explicitly said "performance-wise". The question I was answering
> was:
> Which closer represents the performance of a 64 bit <x> MHz QDR bus?
> (a) A 64-bit <4*x> MHz SDR bus
> (b) A 256-bit <x> MHz SDR bus
> The correct answer is (b).

The correct answer is (a) because that is REALITY. (b) is a figment of your
imagination.


> Of course, at the low level, it's still a 64-bit bus, except one part is
> operating at <x> MHz and another part at <4*x> MHz.

Nope. All the bits of the data arrive at precisely the same rate.

>
> [...]
>
>>>Say you have a 166MHz DDR system
>>>(aka DDR333), and a 100MHz QDR system (aka QDR400), and the CPU runs
>>>at 1GHz (6.0x for DDR, 10.0x for QDR). Excluding memory latencies,
>>>to fill a randomly-accessed 64-byte cache line would take:
>>> Waiting for bus strobe: 3.0 cycles (DDR system), 5.0 cycles (QDR
>>> system) Transferring data: 24 cycles (DDR), 20 cycles (QDR)
>>> Total: 27 cycles (DDR), 25 cycles (QDR)
>>>
>>>So DDR333 is, under random access conditions, only marginally slower
>>>than QDR400. The actual break-even point is 180MHz (actually
>>>slightly above due to memory latencies), but hopefully you get the
>>>idea. Of course, the QDR system will perform better under
>>>"streaming" type conditions, where the higher latency won't matter
>>>so much.
>>
>>No, you're analyzing the memory, not the processor bus.
>
>
> Errm, not at all. I specifically EXCLUDE any memory performance
> considerations from the analysis: see the third line of your quoted section.

You claim to be excluding it but you embed it in your analysis nonetheless.

You also create artificial conditions in direct contrast to reality by, for
example, trying to limit the analysis to 'random access' on a bus that is
specifically designed for, optimized for, and RATED AT it's synchronous
stream transfer rate whether it be SDR, DDR, or QDR.

Heck, the names you (properly) use explain it even as you're denying it:
SRD - Single DATA RATE, DDR - Double DATA RATE, QDR - Quad DATA RATE.


> I'm solely analysing how long it would take to fill (or write out) a
> processor cache line over a DDR/QDR bus, which is pretty much all the
> processor bus is used for.
> The exact same argument applies to the
> point-to-point DDR busses in a K7 SMP system, if having memory in the
> picture makes things confusing for you.

You can wag imaginative theories and pick artificial 'conditions' all you
want. I'm telling you how it works.

>
> [...]
>
>>>Incidentally, this issue is exasparated by the P4's 128-byte cache
>>>line, as opposed to the 64-byte cache line of the K7.
>>
>>Processor (L2) cache has nothing to do with bus speed.
>
>
> Hence my "incidentally" (spot the recurring theme here: I don't usually put
> in words for no reason). The processor cache line size (note: cache LINE
> size, not cache size or anything else) and bus performance characteristics
> are quite interlinked for the performance of a processor. The larger cache
> line size improves streaming performance and decreases random-access
> performance, which is exactly the same characteristics as a QDR bus. My
> point was that the P4 has been heavily tweaked towards streaming
> computations, as opposed to having fast random-access times.

We aren't talking about the "performance of a processor." We're talking
about the bus data rate.

> [...]
>
>>Btw, what don't you call a 3.4 Gig P4 a 200Mhz P4 because the 'real
>>clock' (sic) is 200 Mhz. That 3.4 Gig number is just 'hype'.
>
>
> Why don't you call it a 6.8GHz P4? :p

Because the reality of it is that it's operating at 3.4 GHz.

> I call it a 3.4GHz CPU because it operates on a 3.4GHz clock rate. The
> external signalling is at 200MHz or 800MHz, but this has not the operating
> frequency of the CPU itself.

Well, close. Yes, it operates at 3.4 Ghz but the "external signaling" is an
irrelevant comment. A 3.4 Gig processor is a 3.4 Gig processor regardless
of the bus speed or even what external clock it derives it's internal clock
from; as long as the internal clock ends up at 3.4 Ghz. And it doesn't
matter if it comes from single pumping, dual pumping, quad pumping, hex
pumping, or any other multiplier of the external clock.

> DDR/QDR is a much trickier problem, as part of
> it is operating at 200MHz, and another part at 800MHz.

Nope, and it's not tricky at all. A 166.6 MHz clocked DDR bus has a stream
rate of 333 million data cycles per second and a 200 MHz clocked Quad
pumped bus has a stream rate of 800 million data cycles per second. Which,
btw, is independednt of the bus width.

Hertz is the synonym of "cycles per second." I.E. In the above examples,
the DDR bus has a 333 MHz data rate and the QDR bus has an 800MHz data
rate; which happens to be the way they are typically rated.


> Sort of as if the
> ALUs all operated at 6.8GHz and the floating point units all operated at
> 3.4GHz. Oh, dearie me ...

The problem is you want everything to be a 'waveform' and that just isn't
the case. And, btw, not every signal in a 3.4 GHz processor is jumping
around at 3.4Ghz either: that's just the clock rate.

>
> [...]
>
> --
> Michael Brown
> www.emboss.co.nz : OOS/RSI software and more :)
> Add michael@ to emboss.co.nz - My inbox is always open
>
>
 
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Archived from groups: alt.comp.hardware.overclocking (More info?)

Well, not really. How about FM modulation, as in FM broadcast radio? The
original carrier frequency is measured in MHz, but then it is modulated by
an audio frequency, measured in KHz, and the results is a varying frequency,
giving a waveform which does not necessarily EVER repeat itself. And then
there is phase modulation, pulse width modulation, not to mention
polarization. And what about "spread spectrum", as used to be found as a
BIOS settings, giving a modulated clock rate? Don't try to read too much
into brief definition.

As clock pulse trains, they carry no more data than a 60 Hz or 50 Hz power
line.

--
Phil Weldon, pweldonatmindjumpdotcom
For communication,
replace "at" with the 'at sign'
replace "mindjump" with "mindspring."
replace "dot" with "."


"BigBadger" <big_badger@NOSPAM.com> wrote in message
news:c56p7j$j12$1@newsg3.svr.pol.co.uk...
> >
> Hertz is a measure of Mega Cycles per second...we both agree on that.
> The dictionary 'physics' definition of a cycle is:
> one complete oscillation: one complete continuous change in the magnitude
of
> an oscillating quantity or system that brings the system back to its
> original energy state.
> Therefore it does not matter how many data points is carried on the wave,
> the frequency is the number of cycles (or oscillations) per second and for
> an XP2800+ this is 166,600,000....or 166MHz
>
>
>