Memory timing question?

Archived from groups: alt.comp.hardware.overclocking (More info?)

Hi,

Just looking for a little help on understanding tRAS settings. I found this
article
http://www.mushkin.com/mushkin/pop-up/latencies.htm

that states

Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory
controller to close the page “in your face!” over and again and that will
cause a performance hit because of a truncated transfer that needs to be
repeated.........................

After reading numerous posts I don't find many people following these
recommendations. Has anyone tested tRAS setting changes alone on there
system and could confirm whether or not this is a good rule of thumb?

Thanks in advance
John
1 answer Last reply
More about memory timing question
  1. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "John" <none@jumo.non> wrote in
    news:i5Ipc.43138$L8.20068@nwrdny02.gnilink.net:

    > Hi,
    >
    > Just looking for a little help on understanding tRAS settings. I found
    > this article
    > http://www.mushkin.com/mushkin/pop-up/latencies.htm
    >
    > that states
    >
    > Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory
    > controller to close the page “in your face!” over and again and that
    > will cause a performance hit because of a truncated transfer that
    > needs to be repeated.........................
    >
    > After reading numerous posts I don't find many people following these
    > recommendations. Has anyone tested tRAS setting changes alone on there
    > system and could confirm whether or not this is a good rule of thumb?
    >
    > Thanks in advance
    > John
    >
    >
    >

    I read/wondered same. My Kingston is supposed to be 2-3-2-6-1, but 3+2+2
    ain't quite 6.

    --
    Peder (Please reply to group only, email invalid)
Ask a new question

Read More

Overclocking Memory