fsb speed - why does it matter?

Archived from groups: alt.comp.hardware.overclocking (More info?)

it seems to me that nobody needs a high fsb. since they could just
push the multiplier really high.

I can see the greatness of ddr since the same speed processor can
read/write twice as much per cycle. (i assume that the cpu has to be
ddr to receive or write double)
50 answers Last reply
More about speed matter
  1. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:

    > it seems to me that nobody needs a high fsb. since they could just
    > push the multiplier really high.
    >
    > I can see the greatness of ddr since the same speed processor can
    > read/write twice as much per cycle. (i assume that the cpu has to be
    > ddr to receive or write double)

    How is it you can see the benefit to 'read/write twice as much per cycle'
    yet not see any benefit to more of the cycles?

    The CPU communicates to everything through the FSB, and that includes the
    memory, so the speed of it directly affects how fast the processor can
    communicate. And since the vast majority of that communication is fetching
    instructions from memory, it affects how fast it can process them.
  2. Archived from groups: alt.comp.hardware.overclocking (More info?)

    > it seems to me that nobody needs a high fsb. since they could just
    > push the multiplier really high.
    >


    you cant push the multiplier high because its locked on most modern CPU's

    also higher FSB = higher bandwidth = higher performance.

    --
    From Adam Webb, Overlag
    www.tacticalgamer.com
    CS:SOURCE server now active :D
    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    news:930a4bf.0410290627.3ae70dde@posting.google.com...


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  3. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    news:930a4bf.0410290627.3ae70dde@posting.google.com...
    > it seems to me that nobody needs a high fsb. since they could just
    > push the multiplier really high.

    LOL and what about the locked multipliers on the majority of processors?
  4. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Glitch" <glitch_120@yahoo.com> wrote in message news:<cltte9$bs9$1@bagan.srce.hr>...
    > "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    > news:930a4bf.0410290627.3ae70dde@posting.google.com...
    > > it seems to me that nobody needs a high fsb. since they could just
    > > push the multiplier really high.
    >
    > LOL and what about the locked multipliers on the majority of processors?

    well, AMD can be unlocked. Maybe intel can. They are not really
    'locked' they are 'locked' for people that don't know how to unlock
    them.
    Just as windows files are 'hidden', it's just a gimmick to make it
    'harder'.

    > LOL
    I fail to see the joke
  5. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    > James Hanley wrote:
    >
    > > it seems to me that nobody needs a high fsb. since they could just
    > > push the multiplier really high.
    > >
    > > I can see the greatness of ddr since the same speed processor can
    > > read/write twice as much per cycle. (i assume that the cpu has to be
    > > ddr to receive or write double)
    >
    > How is it you can see the benefit to 'read/write twice as much per cycle'
    > yet not see any benefit to more of the cycles?
    >
    > The CPU communicates to everything through the FSB, and that includes the
    > memory, so the speed of it directly affects how fast the processor can
    > communicate. And since the vast majority of that communication is fetching
    > instructions from memory, it affects how fast it can process them.

    The FSB is not THE ONLY THING that affects the speed. The
    Multiplier*FSB create the speed. The Processor multiplies the FSB,
    and the RAM multiplies the FSB. I am saying that the multiplier can
    be increased, so low FSB speed doesn't matter.
  6. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    > James Hanley wrote:
    >
    > > it seems to me that nobody needs a high fsb. since they could just
    > > push the multiplier really high.
    > >
    > > I can see the greatness of ddr since the same speed processor can
    > > read/write twice as much per cycle. (i assume that the cpu has to be
    > > ddr to receive or write double)
    >
    > How is it you can see the benefit to 'read/write twice as much per cycle'
    > yet not see any benefit to more of the cycles?

    Obviously I see the benefit of more cycles. What do you think I meant
    when I said "push the multiplier really high". That increases the
    cycles per second.
  7. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Adam Webb" <adam@ajmysecondname.eclipse.co.uk> wrote in message news:<QqOdnX9R5pNixx_cRVnygQ@eclipse.net.uk>...
    > > it seems to me that nobody needs a high fsb. since they could just
    > > push the multiplier really high.
    > >
    >
    >
    > you cant push the multiplier high because its locked on most modern CPU's

    nobody on an overclocking forum should be saying
    "oh no, the multiplier is locked, what am I going to do"
    Just like no technician is going to say, oh no, the file is 'hidden'
    what am I going to do

    > also higher FSB = higher bandwidth = higher performance.

    yeah, if it's greater width. i'm talking about speed only though.
  8. Archived from groups: alt.comp.hardware.overclocking (More info?)

    >well, AMD can be unlocked. Maybe intel can. They are not really
    >'locked' they are 'locked' for people that don't know how to unlock
    >them.
    OK Then, Tell us how to unlock the multiplier on the newer locked
    CPUs.

    >Just as windows files are 'hidden', it's just a gimmick to make it
    >'harder'.
    Apples and Oranges there.

    >
    >> LOL
    >I fail to see the joke

    ----------------------------------------------------------------------

    You should start drinking prune juice and KY jelly cocktails right now,
    that will make things a lot smoother.
    -Felatio Love
  9. Archived from groups: alt.comp.hardware.overclocking (More info?)

    >Obviously I see the benefit of more cycles. What do you think I meant
    >when I said "push the multiplier really high". That increases the
    >cycles per second.

    CPU cycles = yes, memory frequency = no. Only raising the FSB
    increases the speed at which the CPU can access the memory.
    ----------------------------------------------------------------------

    You should start drinking prune juice and KY jelly cocktails right now,
    that will make things a lot smoother.
    -Felatio Love
  10. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >>
    >>
    >>>it seems to me that nobody needs a high fsb. since they could just
    >>>push the multiplier really high.
    >>>
    >>>I can see the greatness of ddr since the same speed processor can
    >>>read/write twice as much per cycle. (i assume that the cpu has to be
    >>>ddr to receive or write double)
    >>
    >>How is it you can see the benefit to 'read/write twice as much per cycle'
    >>yet not see any benefit to more of the cycles?
    >>
    >>The CPU communicates to everything through the FSB, and that includes the
    >>memory, so the speed of it directly affects how fast the processor can
    >>communicate. And since the vast majority of that communication is fetching
    >>instructions from memory, it affects how fast it can process them.
    >
    >
    > The FSB is not THE ONLY THING that affects the speed. The
    > Multiplier*FSB create the speed. The Processor multiplies the FSB,

    I didn't say a thing about the CPU speed. I was talking about the FSB: the
    'point' of the discussion. And, as I said, the only means the CPU has to
    COMMUNICATE to anything, including the memory, is through the FSB.

    Just how fast do you think it can get instructions to execute if you turned
    the FSB down to 1 Hz, eh?

    It doesn't make any difference how fast the CPU can execute instructions if
    you can't feed it the instructions to execute.

    > and the RAM multiplies the FSB.

    No. It doesn't 'multiply' the FSB. It operates at the memory bus clock rate.

    > I am saying that the multiplier can
    > be increased, so low FSB speed doesn't matter.

    You missed the entire point, and are incorrect.
  11. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:

    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >>
    >>
    >>>it seems to me that nobody needs a high fsb. since they could just
    >>>push the multiplier really high.
    >>>
    >>>I can see the greatness of ddr since the same speed processor can
    >>>read/write twice as much per cycle. (i assume that the cpu has to be
    >>>ddr to receive or write double)
    >>
    >>How is it you can see the benefit to 'read/write twice as much per cycle'
    >>yet not see any benefit to more of the cycles?
    >
    >
    > Obviously I see the benefit of more cycles. What do you think I meant
    > when I said "push the multiplier really high". That increases the
    > cycles per second.

    No, increasing the multiplier does NOT increase the FSB cycles.
  12. Archived from groups: alt.comp.hardware.overclocking (More info?)

    GTD <duh@stoopid.net> wrote in message news:<p7g8o0tc1hmgsf01s8gtentv5igpg8otml@4ax.com>...
    > >Obviously I see the benefit of more cycles. What do you think I meant
    > >when I said "push the multiplier really high". That increases the
    > >cycles per second.
    >
    > CPU cycles = yes, memory frequency = no. Only raising the FSB
    > increases the speed at which the CPU can access the memory.
    > ----------------------------------------------------------------------

    memory frequency can be increased to a multiple of the FSB even before
    DDR is 'applied'. I have an option in my BIOS to set my DDR-SDRAM
    frequency, I can set my FSB to 100 and my SDRAM to 266 (effective).
    So my actual RAM speed is operating at a frequency of 133 internally,
    which is FSB*(5/4). I don't know if it uses its own multiplier to do
    that, I think it probably does.
    So both RAM and CPU can operate at a frequency that is a multiple of
    the FSB.
    So memory frequency can be increased without increasing the FSB.

    However, against me, I will say that it just occurred to me that the
    speed at which the CPU and RAM interfaces with the FSB is still going
    to be the speed of the FSB, regardless of how high their internals
    speeds are. Thus if one were to weigh doubling the FSB against
    doubling the Multiplier(timesing the current value of the multiplier
    by 2), they would find that doubling the FSB makes for a faster
    computer, since it would have doubled not just both the internal
    frequency of the CPU and RAM - thus their bandwidth, but the speed
    and thus bandwidth of the bus.

    (i'm assuming bandwidth=throughput, but I cannot check at this moment,
    since I'm leaving in a minute, so I have to click Send now!!

    Thanks for your response.
  13. Archived from groups: alt.comp.hardware.overclocking (More info?)

    On 31 Oct 2004 04:21:20 -0800, jameshanley39@yahoo.co.uk (James
    Hanley) wrote:

    >GTD <duh@stoopid.net> wrote in message news:<p7g8o0tc1hmgsf01s8gtentv5igpg8otml@4ax.com>...
    >> >Obviously I see the benefit of more cycles. What do you think I meant
    >> >when I said "push the multiplier really high". That increases the
    >> >cycles per second.
    >>
    >> CPU cycles = yes, memory frequency = no. Only raising the FSB
    >> increases the speed at which the CPU can access the memory.
    >> ----------------------------------------------------------------------
    >
    >memory frequency can be increased to a multiple of the FSB even before
    >DDR is 'applied'. I have an option in my BIOS to set my DDR-SDRAM
    >frequency, I can set my FSB to 100 and my SDRAM to 266 (effective).
    >So my actual RAM speed is operating at a frequency of 133 internally,
    >which is FSB*(5/4). I don't know if it uses its own multiplier to do
    >that, I think it probably does.
    >So both RAM and CPU can operate at a frequency that is a multiple of
    >the FSB.
    >So memory frequency can be increased without increasing the FSB.
    Yes, that is correct

    >
    >However, against me, I will say that it just occurred to me that the
    >speed at which the CPU and RAM interfaces with the FSB is still going
    >to be the speed of the FSB, regardless of how high their internals
    >speeds are.
    Yes, that is what I was trying to articulate. I forgot about the
    presence of FSB/Memory Dividers

    > Thus if one were to weigh doubling the FSB against
    >doubling the Multiplier(timesing the current value of the multiplier
    >by 2), they would find that doubling the FSB makes for a faster
    >computer, since it would have doubled not just both the internal
    >frequency of the CPU and RAM - thus their bandwidth, but the speed
    >and thus bandwidth of the bus.
    >
    >(i'm assuming bandwidth=throughput, but I cannot check at this moment,
    >since I'm leaving in a minute, so I have to click Send now!!
    >
    >Thanks for your response.

    ----------------------------------------------------------------------

    You should start drinking prune juice and KY jelly cocktails right now,
    that will make things a lot smoother.
    -Felatio Love
  14. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > "Adam Webb" <adam@ajmysecondname.eclipse.co.uk> wrote in message
    > news:<QqOdnX9R5pNixx_cRVnygQ@eclipse.net.uk>...
    >>> it seems to me that nobody needs a high fsb. since they could just
    >>> push the multiplier really high.
    >>
    >> you cant push the multiplier high because its locked on most modern
    >> CPU's
    >
    > nobody on an overclocking forum should be saying
    > "oh no, the multiplier is locked, what am I going to do"
    > Just like no technician is going to say, oh no, the file is 'hidden'
    > what am I going to do.

    Better analogy: the technician saying "oh no, someone has wiped the disk
    then turned it into slag in a blast furnace, what am I going to do?". Given
    that people have spent close to 6 years trying to unlock Intel CPUs (no
    success) and about 1 year trying to unlock locked AMD chips (no success), I
    doubt there's going to be much progress on either front. The general view is
    that both companies are using fuses inside the die, which can't be altered
    once set.

    >> also higher FSB = higher bandwidth = higher performance.
    >
    > yeah, if it's greater width. i'm talking about speed only though.

    Umm, say what? It's obvious that more throughput = more performance, and
    throughput = bus width * bus speed, so increasing the bus speed (FSB)
    obviously increases performance. Or do you think a Athlon running sync with
    PC66 RAM (66MHz FSB, SDR, 64 bits wide) would perform just as well as the
    identical CPU running sync with PC3200 RAM (200MHz FSB, DDR, 64 bits wide)?

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
  15. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Michael Brown" <see@signature.below> wrote in message news:<SOUgd.1267$op3.55721@news.xtra.co.nz>...
    > James Hanley wrote:
    > > "Adam Webb" <adam@ajmysecondname.eclipse.co.uk> wrote in message
    > > news:<QqOdnX9R5pNixx_cRVnygQ@eclipse.net.uk>...
    > >>> it seems to me that nobody needs a high fsb. since they could just
    > >>> push the multiplier really high.
    > >>
    > >> you cant push the multiplier high because its locked on most modern
    > >> CPU's
    > >
    > > nobody on an overclocking forum should be saying
    > > "oh no, the multiplier is locked, what am I going to do"
    > > Just like no technician is going to say, oh no, the file is 'hidden'
    > > what am I going to do.
    >
    > Better analogy: the technician saying "oh no, someone has wiped the disk
    > then turned it into slag in a blast furnace, what am I going to do?". Given
    > that people have spent close to 6 years trying to unlock Intel CPUs (no
    > success) and about 1 year trying to unlock locked AMD chips (no success),

    6 years? - but there are loads of articles on unlocking AMD chips, i'm
    sure I think I saw one for the AMD XP 1500+, that's less than 6 years
    old isn't it?

    >The general view is
    > that both companies are using fuses inside the die, which can't be altered
    > once set.

    bastards.
    So how can anybody overclock? Just by upping the FSB to whatever the
    mobo supports?
    I suppose that a CPU will have a built in multiplier at a fixed value,
    and will assume a certain FSB speed. So if the FSB is lower then it's
    underclocked. If it's higher then it's overclocked. Or does it not
    even derive its clock by multiplying the FSB clock?
    Would most people have the FSB at the highest setting suported anyway,
    and they'd have a CPU that supports it, so how would they overclock?
    (they cna't up the FSB clock because it's already on the highest, and
    they can't up the multiplier because it's properly locked)

    > >> also higher FSB = higher bandwidth = higher performance.
    > >
    > > yeah, if it's greater width. i'm talking about speed only though.
    >
    > Umm, say what? It's obvious that more throughput = more performance, and
    > throughput = bus width * bus speed, so increasing the bus speed (FSB)
    > obviously increases performance. Or do you think a Athlon running sync with
    > PC66 RAM (66MHz FSB, SDR, 64 bits wide) would perform just as well as the
    > identical CPU running sync with PC3200 RAM (200MHz FSB, DDR, 64 bits wide)?

    oh yeah, I just realised that in a post in reply to that other Geezer
    in the thread.
    btw, Some software tells me that my RAM is operating at a multiple of
    the processor speed. I can put my FSB=100 and have 266MHZ
    DDR-SDRAM(actual speed 133MHz) So si sandra tells me it's a multiple
    of my FSB.
    Is it correct that RAM uses a multiplier too? It sure looks like it
    from si sandra, though there is no option in the BIOS to set it, I can
    only set the ram frequency. I thought that RAM derives its speed from
    the FSB, the FSB is like the base clock, so it must multiply it,
    strange that there's no option in the bios to set the ram multiplier.
  16. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8u0kk4kphbbd@corp.supernews.com>...
    > James Hanley wrote:
    >
    > > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    > >
    > >>James Hanley wrote:
    > >>
    > >>
    > >>>it seems to me that nobody needs a high fsb. since they could just
    > >>>push the multiplier really high.
    > >>>
    > >>>I can see the greatness of ddr since the same speed processor can
    > >>>read/write twice as much per cycle. (i assume that the cpu has to be
    > >>>ddr to receive or write double)
    > >>
    > >>How is it you can see the benefit to 'read/write twice as much per cycle'
    > >>yet not see any benefit to more of the cycles?
    > >
    > >
    > > Obviously I see the benefit of more cycles. What do you think I meant
    > > when I said "push the multiplier really high". That increases the
    > > cycles per second.
    >
    > No, increasing the multiplier does NOT increase the FSB cycles.

    I knew that, it increases cycles per second, but just CPU cycles.
    So yeah. I just realised that:
    Increasing the multiplier increases CPU cycles (not FSB cycles of
    course).
    Increasing the FSB increases both - that is what hadn't occurred to me
    :P

    So if the system supported it(processor was unlocked and very
    underclocked) doubling the FSB is better than doubling the current
    value of the multiplier. It's better to have a faster FSB(thus
    increasing CPU cycles and FSB cycles) than to have a slower FSB and a
    larger multiplier, which would only increase CPU cycles.

    More CPU cycles --> more CPU bandwidth
    More FSB cycles --> more FSB bandwidth

    I suppose bandwidth and throughput are the same thing


    thanks for your response
  17. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8ttn1rsqsm79@corp.supernews.com>...
    > James Hanley wrote:
    > > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    > >
    > >>James Hanley wrote:
    > >>
    > >>
    <snip>

    > Just how fast do you think it can get instructions to execute if you turned
    > the FSB down to 1 Hz, eh?
    > It doesn't make any difference how fast the CPU can execute instructions if
    > you can't feed it the instructions to execute.

    I was wrong on that one. thanks for your response

    > > and the RAM multiplies the FSB.
    >
    > No. It doesn't 'multiply' the FSB. It operates at the memory bus clock rate.

    Ok. The thing that made me think it multiplied the FSB was
    a)If my memory serves me correctly, Si Sandra lists alongside the
    actual and effective memory clock speeds, a multiple, which seems to
    work out the actual memory speed correctly if taken as a multiple of
    the actual fsb speed.
    b)the FSB is often called the base clock, since - i've been told - all
    clocks in the system are derived from it - thus, I thought maybe the
    memory clock speed was derived from it too (with a multiplier).

    I can accept that si sandra is being misleading and that the clock is
    independent, since the BIOS does not have a setting to change any
    'memory multiplier'.

    Maybe the thing I had been told that "all clocks in the system are
    derived from the base clock - fsb clock" is wrong, and should read
    "all clocks in the system are synchronized with the base/fsb clock"


    So the FSB has its own clock, the Synchronous Memory has its own
    clock.
    But the PCI, AGP and CPU have a derived clock? (I make this
    statement by looking at where in the bios i can set the multiplier)

    thanks
  18. Archived from groups: alt.comp.hardware.overclocking (More info?)

    try unlocking an A64 or a P3/P4

    XP's yeah sure you can unlock them, but why? the higher the fsb the better

    --
    From Adam Webb, Overlag
    www.tacticalgamer.com
    CS:SOURCE server now active :D
    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    news:930a4bf.0410310817.50f2267e@posting.google.com...
    > "Michael Brown" <see@signature.below> wrote in message
    news:<SOUgd.1267$op3.55721@news.xtra.co.nz>...
    > > James Hanley wrote:
    > > > "Adam Webb" <adam@ajmysecondname.eclipse.co.uk> wrote in message
    > > > news:<QqOdnX9R5pNixx_cRVnygQ@eclipse.net.uk>...
    > > >>> it seems to me that nobody needs a high fsb. since they could just
    > > >>> push the multiplier really high.
    > > >>
    > > >> you cant push the multiplier high because its locked on most modern
    > > >> CPU's
    > > >
    > > > nobody on an overclocking forum should be saying
    > > > "oh no, the multiplier is locked, what am I going to do"
    > > > Just like no technician is going to say, oh no, the file is 'hidden'
    > > > what am I going to do.
    > >
    > > Better analogy: the technician saying "oh no, someone has wiped the disk
    > > then turned it into slag in a blast furnace, what am I going to do?".
    Given
    > > that people have spent close to 6 years trying to unlock Intel CPUs (no
    > > success) and about 1 year trying to unlock locked AMD chips (no
    success),
    >
    > 6 years? - but there are loads of articles on unlocking AMD chips, i'm
    > sure I think I saw one for the AMD XP 1500+, that's less than 6 years
    > old isn't it?
    >
    > >The general view is
    > > that both companies are using fuses inside the die, which can't be
    altered
    > > once set.
    >
    > bastards.
    > So how can anybody overclock? Just by upping the FSB to whatever the
    > mobo supports?
    > I suppose that a CPU will have a built in multiplier at a fixed value,
    > and will assume a certain FSB speed. So if the FSB is lower then it's
    > underclocked. If it's higher then it's overclocked. Or does it not
    > even derive its clock by multiplying the FSB clock?
    > Would most people have the FSB at the highest setting suported anyway,
    > and they'd have a CPU that supports it, so how would they overclock?
    > (they cna't up the FSB clock because it's already on the highest, and
    > they can't up the multiplier because it's properly locked)
    >
    > > >> also higher FSB = higher bandwidth = higher performance.
    > > >
    > > > yeah, if it's greater width. i'm talking about speed only though.
    > >
    > > Umm, say what? It's obvious that more throughput = more performance, and
    > > throughput = bus width * bus speed, so increasing the bus speed (FSB)
    > > obviously increases performance. Or do you think a Athlon running sync
    with
    > > PC66 RAM (66MHz FSB, SDR, 64 bits wide) would perform just as well as
    the
    > > identical CPU running sync with PC3200 RAM (200MHz FSB, DDR, 64 bits
    wide)?
    >
    > oh yeah, I just realised that in a post in reply to that other Geezer
    > in the thread.
    > btw, Some software tells me that my RAM is operating at a multiple of
    > the processor speed. I can put my FSB=100 and have 266MHZ
    > DDR-SDRAM(actual speed 133MHz) So si sandra tells me it's a multiple
    > of my FSB.
    > Is it correct that RAM uses a multiplier too? It sure looks like it
    > from si sandra, though there is no option in the BIOS to set it, I can
    > only set the ram frequency. I thought that RAM derives its speed from
    > the FSB, the FSB is like the base clock, so it must multiply it,
    > strange that there's no option in the bios to set the ram multiplier.


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  19. Archived from groups: alt.comp.hardware.overclocking (More info?)

    > Obviously I see the benefit of more cycles. What do you think I meant
    > when I said "push the multiplier really high". That increases the
    > cycles per second.

    theres no point having a 2000mhz CPU if its connection to the rest of the
    system is only 100mhz.

    if the ram is running at 200mhz, and the fsb is running at 100mhz do you
    really think it gets max performance out of the ram? no it just sits there
    waiting for stuff to do, exaclty what the CPU does also, sure it can do
    stuff at 2000mhz but it has to send it down a small 100mhz pipe, dont you
    think thats a rather SLOW way of doing things?

    the fsb is the limit on todays systems hence the reason for pushing it so
    high, id much rather have a 8x250 than a 10x200 A64 system.


    Oh and about the locks:

    Intel P3 and P4s can not be unlocked (ES dont count)
    A64s cant go up on multiplyers, just down.
    FX's are totaly unlocked.
    2003 week >39 XP's are unlockable, but alittle harder than before
    2003 week <39 XP's are unlockable with ease.


    --
    From Adam Webb, Overlag
    www.tacticalgamer.com
    CS:SOURCE server now active :D


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  20. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8u0kk4kphbbd@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >>
    >>
    >>>David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    >>>
    >>>
    >>>>James Hanley wrote:
    >>>>
    >>>>
    >>>>
    >>>>>it seems to me that nobody needs a high fsb. since they could just
    >>>>>push the multiplier really high.
    >>>>>
    >>>>>I can see the greatness of ddr since the same speed processor can
    >>>>>read/write twice as much per cycle. (i assume that the cpu has to be
    >>>>>ddr to receive or write double)
    >>>>
    >>>>How is it you can see the benefit to 'read/write twice as much per cycle'
    >>>>yet not see any benefit to more of the cycles?
    >>>
    >>>
    >>>Obviously I see the benefit of more cycles. What do you think I meant
    >>>when I said "push the multiplier really high". That increases the
    >>>cycles per second.
    >>
    >>No, increasing the multiplier does NOT increase the FSB cycles.
    >
    >
    > I knew that, it increases cycles per second, but just CPU cycles.
    > So yeah. I just realised that:
    > Increasing the multiplier increases CPU cycles (not FSB cycles of
    > course).
    > Increasing the FSB increases both - that is what hadn't occurred to me
    > :P

    It isn't because of increasing 'both': that's a matter of the CPU
    multiplier being locked, or not.

    A 1.83 Ghz processor on a 333 Mhz FSB will perform better than a 1.83 Ghz
    processor running on a 266 Mhz FSB, whether you accomplish the test by
    buying two different processors or using one with an adjustable multiplier.

    It isn't as dramatic an improvement as changing the CPU speed (multiplier)
    partly because it's offset by the L2 cache.


    > So if the system supported it(processor was unlocked and very
    > underclocked) doubling the FSB is better than doubling the current
    > value of the multiplier.

    It depends on what you mean by that.

    If you mean taking a processor of speed X on FSB Y and *either* doubling
    the FSB *or* doubling the CPU speed then no, doubling the FSB, alone, is
    not as good as doubling the CPU speed, alone.

    If you mean, as I suspect you do, doing one or the other to end up with the
    same CPU speed after it's all said and done, then yes, because a processor
    at speed X will perform better if it also has a faster FSB (within reason).

    Let's put it to a practical example. I have an unlocked mobile Barton 2400
    on a DFI motherboard that let's me adjust everything, so I can run it
    overclocked to 2.2 Ghz at 266 Mhz FSB, 333 Mhz FSB, or 400 Mhz FSB (if I
    stay at 'standard' FSBs) by adjusting the multiplier accordingly. Which do
    you think will give me the best performance?

    > It's better to have a faster FSB(thus
    > increasing CPU cycles and FSB cycles) than to have a slower FSB and a
    > larger multiplier, which would only increase CPU cycles.

    You're mixing apples and oranges. In one case you alter the CPU speed but
    not in the other. That might be a constraint imposed when using a locked
    multiplier CPU but it confuses the matter that increasing the FSB, alone,
    improves processor performance because more instructions can get to it per
    second.

    >
    > More CPU cycles --> more CPU bandwidth

    No. More 'CPU cycles' (all else being equal) ---> more instructions
    executed per second, assuming it can GET the instructions at that rate.

    > More FSB cycles --> more FSB bandwidth
    >
    > I suppose bandwidth and throughput are the same thing

    Bandwidth is capability and throughput is what is actually going through.

    >
    > thanks for your response
  21. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:

    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8ttn1rsqsm79@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >>
    >>>David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    >>>
    >>>
    >>>>James Hanley wrote:
    >>>>
    >>>>
    >
    > <snip>
    >
    >>Just how fast do you think it can get instructions to execute if you turned
    >>the FSB down to 1 Hz, eh?
    >>It doesn't make any difference how fast the CPU can execute instructions if
    >>you can't feed it the instructions to execute.
    >
    >
    > I was wrong on that one. thanks for your response
    >
    >
    >>>and the RAM multiplies the FSB.
    >>
    >>No. It doesn't 'multiply' the FSB. It operates at the memory bus clock rate.
    >
    >
    > Ok. The thing that made me think it multiplied the FSB was
    > a)If my memory serves me correctly, Si Sandra lists alongside the
    > actual and effective memory clock speeds, a multiple, which seems to
    > work out the actual memory speed correctly if taken as a multiple of
    > the actual fsb speed.
    > b)the FSB is often called the base clock, since - i've been told - all
    > clocks in the system are derived from it - thus, I thought maybe the
    > memory clock speed was derived from it too (with a multiplier).

    Well, more like 'system clock' but it, itself, is 'multiplied' from a lower
    clock.

    The point I was making is that there is no 'multiplier' *in* memory sticks,
    as there is with the processor. Memory simply runs at the speed of the bus
    it's on.

    Typically the memory bus operated at the same speed as the FSB but modern
    northbridge implementations often allow for running it at some 'ratio' to
    the FSB. That 'not the same as FSB' memory bus clock is generated by the
    northbridge and it's not a 'memory' clock, as in the sense of the CPU, it's
    a memory *bus* clock.

    "Multiplier" has multiple (pun) meanings. One refers to a mathematical
    relationship. I.E. 266 is 2 times 133. The other refers to how that number
    is physically implemented in the hardware.

    While DDR is 'x2' SDR, in terms of theoretical bandwidth, it is not done by
    'multiplying' a 133 Mhz clock to get a 266 Mhz clock. It is accomplished by
    sending data on both the leading and trailing edges of the same, as SDR, clock.

    I.E. | 1 cycle |
    ____ ____
    | | | |
    clock --- ---- ---

    | | | |
    SDR Data | Data |
    | | | |
    DDR Data Data Data Data

    The clock speed is the same and there is no 'multiplier' creating a new,
    'double speed' clock. Yet the effective speed is '2x' because it sends the
    data twice per clock.

    The CPU *does* have a 'multiplier'.

    I.E. __________________Processor Package_______________
    | |
    System | |
    clock --> CPU pin --> phase lock loop --> internal CPU clock |
    | ^ |
    | | |
    | multiplier |
    |__________________________________________________|

    The internal CPU clock operates at xMultiplier the external clock.


    > I can accept that si sandra is being misleading and that the clock is
    > independent, since the BIOS does not have a setting to change any
    > 'memory multiplier'.

    I'm not sure what 'significance' you're trying to ascribe to 'derived' vs
    'independent'.


    > Maybe the thing I had been told that "all clocks in the system are
    > derived from the base clock - fsb clock" is wrong, and should read
    > "all clocks in the system are synchronized with the base/fsb clock"

    It's an oversimplification that ignores what part of the system is doing
    what and why.

    > So the FSB has its own clock, the Synchronous Memory has its own
    > clock.

    It's both 'their own clock' and derived.

    > But the PCI, AGP and CPU have a derived clock? (I make this
    > statement by looking at where in the bios i can set the multiplier)


    >
    > thanks
  22. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:

    > "Michael Brown" <see@signature.below> wrote in message news:<SOUgd.1267$op3.55721@news.xtra.co.nz>...
    >
    >>James Hanley wrote:
    >>
    >>>"Adam Webb" <adam@ajmysecondname.eclipse.co.uk> wrote in message
    >>>news:<QqOdnX9R5pNixx_cRVnygQ@eclipse.net.uk>...
    >>>
    >>>>>it seems to me that nobody needs a high fsb. since they could just
    >>>>>push the multiplier really high.
    >>>>
    >>>>you cant push the multiplier high because its locked on most modern
    >>>>CPU's
    >>>
    >>>nobody on an overclocking forum should be saying
    >>>"oh no, the multiplier is locked, what am I going to do"
    >>>Just like no technician is going to say, oh no, the file is 'hidden'
    >>>what am I going to do.
    >>
    >>Better analogy: the technician saying "oh no, someone has wiped the disk
    >>then turned it into slag in a blast furnace, what am I going to do?". Given
    >>that people have spent close to 6 years trying to unlock Intel CPUs (no
    >>success) and about 1 year trying to unlock locked AMD chips (no success),
    >
    >
    > 6 years? - but there are loads of articles on unlocking AMD chips, i'm
    > sure I think I saw one for the AMD XP 1500+, that's less than 6 years
    > old isn't it?

    You didn't pay attention to what he wrote. The 6 years was with regard to
    Intel processors and he said "about 1 year" with respect to AMD processors.

    >
    >
    >>The general view is
    >>that both companies are using fuses inside the die, which can't be altered
    >>once set.
    >
    >
    > bastards.

    It all started when unscrupulous resellers simply remarked lower speed
    chips to higher speed ones so they could profit by selling cheap processors
    at the higher price.

    > So how can anybody overclock? Just by upping the FSB to whatever the
    > mobo supports?

    Correct. Except that Intel has now tried to lock the FSB.

    > I suppose that a CPU will have a built in multiplier at a fixed value,
    > and will assume a certain FSB speed. So if the FSB is lower then it's
    > underclocked. If it's higher then it's overclocked.

    Correct

    > Or does it not
    > even derive its clock by multiplying the FSB clock?

    It has no other choice.

    > Would most people have the FSB at the highest setting suported anyway,
    > and they'd have a CPU that supports it, so how would they overclock?
    > (they cna't up the FSB clock because it's already on the highest, and
    > they can't up the multiplier because it's properly locked)

    That's why overclockerr's PICK the best processor to overclock, and a
    motherboard that provides the ability to do so.


    <snip>
  23. Archived from groups: alt.comp.hardware.overclocking (More info?)

    Adam Webb wrote:
    [...]
    > Oh and about the locks:
    >
    > Intel P3 and P4s can not be unlocked (ES dont count)
    > A64s cant go up on multiplyers, just down.
    > FX's are totaly unlocked.
    > 2003 week >39 XP's are unlockable, but alittle harder than before

    2003 week >39 XP's are not unlockable. Show me a post week 39 desktop CPU
    running at anything but the default multiplier on a NF2. Or the cache being
    enabled on a post week 39 Duron. You can get around the L3 lock on some
    chipsets by enabling PowerNow, but you certainly can't unlock the chip.

    > 2003 week <39 XP's are unlockable with ease.

    2003 week <39 XP's aren't locked :) Well, I suppose the Palomino is if you
    want to go back that far (and is easily unlockable as you noted).

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
  24. Archived from groups: alt.comp.hardware.overclocking (More info?)

    > > 2003 week >39 XP's are unlockable, but alittle harder than before
    >
    > 2003 week >39 XP's are not unlockable. Show me a post week 39 desktop CPU
    > running at anything but the default multiplier on a NF2. Or the cache
    being
    > enabled on a post week 39 Duron. You can get around the L3 lock on some
    > chipsets by enabling PowerNow, but you certainly can't unlock the chip.

    oooooh they not unlockable at all? i thought there was a hardway to do it? i
    dunno my last XP was a week 20 something ;-)

    --
    From Adam Webb, Overlag
    www.tacticalgamer.com
    CS:SOURCE server now active :D


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  25. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message ...
    > memory frequency can be increased to a multiple of the FSB even
    > before DDR is 'applied'.

    Of course it can. Trouble is that you can do what the hell you like to the
    FSB:memory multiplier, but after a certain point the connection between the
    memory and the processor can't keep up, so your increases in memory speed
    are wasted. What is the point of having, say, 8GB/sec memory bandwidth if
    the link between the memory controller and the CPU only runs at 4GB/sec?

    > I have an option in my BIOS to set my DDR-SDRAM frequency,
    > I can set my FSB to 100 and my SDRAM to 266 (effective).

    Virtually all motherboards do this nowadays. However, you are better off
    keeping a synchronous memory bus and raising the FSB than you are clocking
    the memory bus up and leaving the FSB slower. In both AMD (HyperTransport)
    and Intel (NetBurst Bus) cases, the FSB directly controls the speed of the
    internal processor to memory bus, and only by keeping the bandwidth of this
    bus at least equal to the memory bandwidth can you take full advantage of
    the memory speed.

    This is why both AMD and Intel have been raising the effective FSB of their
    motherboards and processors the last few years. Look at the way Intel went
    from 100 (effective 400MHz QDR) FSB to (soon) 266MHz (effectively 1066MHz).
    The reason they've done it is to allow sufficient headroom for ever faster
    memory to interface optimally with the processor.

    > So both RAM and CPU can operate at a frequency that is a multiple of
    > the FSB.
    > So memory frequency can be increased without increasing the FSB.

    Of course it can. The processor bus speed, by contrast, can only be
    increased by increasing the FSB.

    > (i'm assuming bandwidth=throughput, but I cannot check at this moment,
    > since I'm leaving in a minute, so I have to click Send now!!

    For the purposes of this conversation, bandwidth does equal throughput.
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  26. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    > do dabs pay you to post garbage?

    No, wasn't sure whether you were genuinely ignorant of the issues here, or
    whether you were trolling, so chose to hedge my bets by mildly taking the
    p*ss out of you.
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  27. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" wrote in message
    > 6 years? - but there are loads of articles on unlocking AMD chips,

    Try finding one about unlocking Intel CPU's.

    > i'm sure I think I saw one for the AMD XP 1500+, that's less than 6
    > years old isn't it?

    Read Michael's post again. The six years comment was in reference to Intel
    stuff. The only modern Intel CPU's with variable multipliers are some of the
    very latest Pentium M's and Pentium 4's, and even there the multiplier can't
    be unlocked in the full sense of the word, the chip is shipped with a range
    of multipliers accessible.

    > So how can anybody overclock? Just by upping the FSB to
    > whatever the mobo supports?

    Or whatever the CPU and memory will tolerate, whichever comes first. As has
    been said, locked multipliers aren't a problem, as raising the FSB is the
    best way to do it anyway.

    > I suppose that a CPU will have a built in multiplier at a fixed
    > value

    Correct, with the caveat that on many AMD chips, and old Intel ones, it can
    be changed by one means or another.

    > and will assume a certain FSB speed.

    Yes and no. The manufacturer, whether it be Intel or AMD, will decide on an
    FSB, but rather than the CPU making assumptions, it will *tell* the
    motherboard what FSB to select. Most motherboards with any enthusiast
    pretensions will be able to override this though.

    > So if the FSB is lower then it's underclocked. If it's higher
    > then it's overclocked.

    Yes and yes.

    > Would most people have the FSB at the highest setting suported
    > anyway,

    No way. Most of the people who go out of their way to build an overclocked
    system will deliberately choose a CPU-motherboard-memory platform that
    offers headroom for overclocking. Intel CPU's are a case in point: the
    "slower"/cheaper CPU's with lower multipliers tend to make better
    overclocking candidates than the "faster" ones.

    Most motherboards will run much faster than their officially supported
    speeds anyway. Just look at the old 440BX Pentium II/III chipset, which was
    only ever designed to run at 100MHz FSB, but would, in practice, work
    perfectly stably at 166 or higher. The situation today is no different.
    Intel's Canterwood and Springdale chipsets are designed for operation at
    200MHz FSB, but will in practice run at over 300.

    > (they cna't up the FSB clock because it's already on the highest,
    > and they can't up the multiplier because it's properly locked)

    There's a big difference between the highest speed that's "officially"
    supported by a chipset and what it will do in practice. There are also
    plenty of examples where you might want to buy a "slower" CPU because it
    makes a better overclocking candidate.

    > btw, Some software tells me that my RAM is operating at a multiple
    > of the processor speed. I can put my FSB=100 and have 266MHZ
    > DDR-SDRAM(actual speed 133MHz)

    Trouble with this approach, especially on modern platforms, is that setting
    the memory bus faster than the frontside bus doesn't get you anything, as
    there's a bottleneck in the connection between the memory and the processor,
    which you only raise by raising the FSB.

    > Is it correct that RAM uses a multiplier too?

    Yes.

    > It sure looks like it from si sandra, though there is no option
    > in the BIOS to set it, I can only set the ram frequency.

    It *is* a multiplier, despite the confusing labelling. The "100MHz" setting
    corresponds to a 1:1 FSB:memory bus multiplier. The "133MHz" setting
    corresponds to 1:1.3333 FSB:memory ratio. One thing to add though is that
    you have to be careful with Sandra and taking what she says as gospel, as
    like many women, she often misleads and sometimes downright lies.

    > strange that there's no option in the bios to set the ram multiplier.

    It is exactly that option, it's just that your particular motherboard
    manufacturer has chosen to present it in a slightly different manner. Many
    motherboard makers list it in their BIOSes as what it is - a multiplier (or,
    as is often the case, a divider).
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  28. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    > do dabs pay you to post garbage?

    No, newbie. Have you ever heard the saying "Ask a silly question and you'll
    get a silly answer?"?

    At the time I read your post I wasn't sure whether you were genuinely
    ignorant of the issues at work here or whether you were trolling, so I chose
    to mildly poke fun at you in an attempt to find out.

    If, as another saying goes, you don't like the heat, well, you know what to
    do. If, on the other hand, you want to learn something, wind your neck in a
    little and learn that not all humour is signposted with smileys. In those
    circumstances I'm sure you'll learn a lot.
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  29. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10ob0hd7k1909b9@corp.supernews.com>...
    > James Hanley wrote:
    > > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8u0kk4kphbbd@corp.supernews.com>...
    > >
    > >>James Hanley wrote:
    > >>
    > >>
    > >>>David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    > >>>
    > >>>
    > >>>>James Hanley wrote:
    > >>>>
    > >>>>
    > >>>>
    > >>>>>it seems to me that nobody needs a high fsb. since they could just
    > >>>>>push the multiplier really high.
    > >>>>>
    > >>>>>I can see the greatness of ddr since the same speed processor can
    > >>>>>read/write twice as much per cycle. (i assume that the cpu has to be
    > >>>>>ddr to receive or write double)
    > >>>>
    > >>>>How is it you can see the benefit to 'read/write twice as much per cycle'
    > >>>>yet not see any benefit to more of the cycles?
    > >>>
    > >>>
    > >>>Obviously I see the benefit of more cycles. What do you think I meant
    > >>>when I said "push the multiplier really high". That increases the
    > >>>cycles per second.
    > >>
    > >>No, increasing the multiplier does NOT increase the FSB cycles.
    > >
    > >
    > > I knew that, it increases cycles per second, but just CPU cycles.
    > > So yeah. I just realised that:
    > > Increasing the multiplier increases CPU cycles (not FSB cycles of
    > > course).
    > > Increasing the FSB increases both - that is what hadn't occurred to me
    > > :P
    >
    > It isn't because of increasing 'both': that's a matter of the CPU
    > multiplier being locked, or not.

    Maybe I wasn't clear with what I meant by both. I didn't mean
    multiplier and cpu cycles.

    I meant that increasing the FSB increases both the FSB(naturally!!)
    and the CPU cycles.

    Whilst increasing the multiplier increases only CPU cycles. (the
    increase in the multiplier only serves the CPU speed. But increasing
    the FSB serves not just the CPU, but the FSB, which is an integral
    part of the system)

    I think we're in agreement here, as you say
    "a processor at speed X will perform better if it also has a faster
    FSB (within reason)."
    The value of the multiplier only serves to determine the CPU speed.
    Unlike the FSB. (actrually for a given cpu speed, a higher mnultiplier
    is worse because it implies a lower fsb)

    > A 1.83 Ghz processor on a 333 Mhz FSB will perform better than a 1.83 Ghz
    > processor running on a 266 Mhz FSB, whether you accomplish the test by
    > buying two different processors or using one with an adjustable multiplier.
    >
    > It isn't as dramatic an improvement as changing the CPU speed (multiplier)
    > partly because it's offset by the L2 cache.
    >
    >
    > > So if the system supported it(processor was unlocked and very
    > > underclocked) doubling the FSB is better than doubling the current
    > > value of the multiplier.
    >
    > It depends on what you mean by that.
    >
    > If you mean taking a processor of speed X on FSB Y and *either* doubling
    > the FSB *or* doubling the CPU speed then no, doubling the FSB, alone, is
    > not as good as doubling the CPU speed, alone.
    >
    > If you mean, as I suspect you do, doing one or the other to end up with the
    > same CPU speed after it's all said and done, then yes, because a processor
    > at speed X will perform better if it also has a faster FSB (within reason).

    yep

    > Let's put it to a practical example. I have an unlocked mobile Barton 2400
    > on a DFI motherboard that let's me adjust everything, so I can run it
    > overclocked to 2.2 Ghz at 266 Mhz FSB, 333 Mhz FSB, or 400 Mhz FSB (if I
    > stay at 'standard' FSBs) by adjusting the multiplier accordingly. Which do
    > you think will give me the best performance?
    >
    > > It's better to have a faster FSB(thus
    > > increasing CPU cycles and FSB cycles) than to have a slower FSB and a
    > > larger multiplier, which would only increase CPU cycles.
    >
    > You're mixing apples and oranges. In one case you alter the CPU speed but
    > not in the other.

    we must be misunderstanding each other. In both cases, i.e. whether
    increase
    the FSB or increase the multiplier, it will increase cpu clock speed.

    we agree, that for a given cpu clock speed, a faster FSB is better.
    The higher multiplier does not benefit the system other than
    increasing the cpu clock speed.
    For a given cpu clock speed, a higher multiplier would mean that the
    FSB is lower, which is actually detrimental.

    I'm just saying that for a given cpu clock speed, a higher FSB is
    better. Better than a higher multiplier, since a higher multiplier
    implies a lower FSB.

    >That might be a constraint imposed when using a locked
    > multiplier CPU but it confuses the matter that increasing the FSB, alone,
    > improves processor performance because more instructions can get to it per
    > second.
    >
    > >
    > > More CPU cycles --> more CPU bandwidth
    >
    > No. More 'CPU cycles' (all else being equal) ---> more instructions
    > executed per second, assuming it can GET the instructions at that rate.

    I agree that a faster CPU is not much good if it can't get the
    instructions at that rate. I just thought that the expression 'cpu
    bandwidth' didn't take the fsb into account.
    I erred there. On googling, I just realised that CPU bandwidth
    presumably means the maximum supported FSB bandwidth.

    > > More FSB cycles --> more FSB bandwidth
    > >
    > > I suppose bandwidth and throughput are the same thing
    >
    > Bandwidth is capability and throughput is what is actually going through.
    >
    > >
    > > thanks for your response
  30. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard wrote:
    [...]
    > The CPU *does* have a 'multiplier'.

    Oooo, you're lucky you put that in quotes :P

    __________________Processor Package_______________
    | |
    System | |
    clock --> CPU pin --> phase lock loop --> internal CPU clock |
    | ^ | |
    | | | |
    | divider <------------/ |
    |__________________________________________________|

    Yes, I know I'm being picky :)

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
  31. Archived from groups: alt.comp.hardware.overclocking (More info?)

    Michael Brown wrote:

    > David Maynard wrote:
    > [...]
    >
    >>The CPU *does* have a 'multiplier'.
    >
    >
    > Oooo, you're lucky you put that in quotes :P

    It wasn't 'luck'. I use single quotes to denote irony, the 'colloquial
    gist' (sometimes akin to irony), or non literal use of a word/phrase.

    In that case I was indicating the colloquial gist of the function and not
    necessarily a literal.

    >
    > __________________Processor Package_______________
    > | |
    > System | |
    > clock --> CPU pin --> phase lock loop --> internal CPU clock |
    > | ^ | |
    > | | | |
    > | divider <------------/ |
    > |__________________________________________________|
    >
    > Yes, I know I'm being picky :)

    Technically what you did was break the block diagram down further and show
    how the phase lock loop accomplishes the multiply. Both are appropriate,
    depending on what one is trying to convey: how the multiplier works or
    simply that there's a multiplier.

    >
    > --
    > Michael Brown
    > www.emboss.co.nz : OOS/RSI software and more :)
    > Add michael@ to emboss.co.nz - My inbox is always open
    >
    >
  32. Archived from groups: alt.comp.hardware.overclocking (More info?)

    Adam Webb wrote:
    >>> 2003 week >39 XP's are unlockable, but alittle harder than before
    >>
    >> 2003 week >39 XP's are not unlockable. Show me a post week 39
    >> desktop CPU running at anything but the default multiplier on a NF2.
    >> Or the cache being enabled on a post week 39 Duron. You can get
    >> around the L3 lock on some chipsets by enabling PowerNow, but you
    >> certainly can't unlock the chip.
    >
    > oooooh they not unlockable at all? i thought there was a hardway to
    > do it? i dunno my last XP was a week 20 something ;-)

    The "hard way" is enabling PowerNow on the CPU, and is what people are
    calling psuedo-unlocking of the CPU. It doesn't work on NF1/NF2 chipsets,
    and is only really of use when you've maxed your FSB without maxing out the
    CPU (for example running a Barton 2500 at a good speed on a board that only
    works up to a FSB of 150MHz or so).

    There actually isn't one multiplier setting on the Athlon XP, but two.
    There's the startup multiplier, and the maximum multiplier. When it's
    powered on, the CPU reads the startup multiplier and uses this setting. In a
    desktop CPU (which doesn't have PowerNow), this is where it ends. You're
    stuck with the startup multiplier until you reset the chip. On a mobile CPU
    (or rather, any CPU with PowerNow) things are a bit better. Once the CPU has
    been started, you can transition to any multiplier less than the maximum
    one, as long as the chipset supports PowerNow transitions (pretty much all
    do except the NF1/NF2).

    What AMD did was not "locking the multiplier" per se, but rather storing the
    L3 (and L2, but that's a different thread) bridge configuration inside the
    die. So instead of reading it off the bridges/BP_FID pins on boot, it reads
    it from its internal storage. Noone has figured out how to talk to this
    internal storage, and there's a ery high chance that it's been closed off to
    the outside world. For example, there's quite possibly a bit in the storage
    that says "ignore any attempt to write into the storage". You can't change
    the multiplier (because the "write protect" bit has been set), and you can't
    reset the bit (since this would require writing to the storage, which is
    denied). Or alternatively, if a bit can only be "set", then there could be
    pairs of bits. If both bits are set, then something has been tampered with
    and the CPU would refuse to start. Again, this completely prevents any
    changing of the settings.

    Sooooo, in a locked AMD chip, there's no way to set the startup multiplier,
    and if the CPU doesn't have PowerNow support, then there's no way to change
    the multiplier at all. All K7 BIOSes that I've seen do multiplier
    adjustments through the startup multiplier (messing with the BP_FID pins),
    so once you lock the L3 bridge configuration, you disable the ability of all
    BIOSes to use anything but the stock startup multiplier.

    The "psuedo-unlock" involves activating PowerNow, and setting the maximum
    multiplier to something good. Then, you can make the chip operate at any
    multiplier that you like, though the chip still boots up at the original
    multiplier.

    Currently, the die-storage is only used in desktop CPUs. However, it's clear
    that there's nothing stopping AMD from using it on mobile CPUs as well.
    Mobile systems acheive power saving through PowerNow transitions, not
    manipulation of the startup multiplier, so whether the L3 configuration is
    locked or not makes no difference to them. It's also obvious that there's
    nothing (except possibly technological reasons, such as a limited amount of
    data that can be stored in the die) stopping AMD from putting all the
    bridges inside the die. It's exactly what they do for the K8 chips. It just
    means that
    a) You can't adjust the startup multiplier
    b) You can't adjust the maximim multiplier
    c) You can't enable or disable PowerNow

    None of these restrictions will stop a mobile CPU from working correctly in
    a mobile system. Restrictions "a" and "b" combine to stop the chip running
    at anything over the stock multiplier. Restriction "c" means that a desktop
    CPU will ONLY operate at the startup multiplier and nothing else.

    What do we have today? Well, mobile CPUs have no restrictions. This is good,
    and lets hope it stays this way. Desktop CPUs have restriction "a", which
    means that as long as your board supports PowerNow, you have a bit more
    freedom as to how you run your CPU. However, if you have a NForce chipset
    (which don't support PowerNow transitions), you effectively have restriction
    "c" imposed. Which means that on an NF board, a desktop CPU will only
    operate at it's stock startup multiplier.

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
  33. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10ob0hd7k1909b9@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >>
    >>>David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o8u0kk4kphbbd@corp.supernews.com>...
    >>>
    >>>
    >>>>James Hanley wrote:
    >>>>
    >>>>
    >>>>
    >>>>>David Maynard <dNOTmayn@ev1.net> wrote in message news:<10o4ng1d1f0ct94@corp.supernews.com>...
    >>>>>
    >>>>>
    >>>>>
    >>>>>>James Hanley wrote:
    >>>>>>
    >>>>>>
    >>>>>>
    >>>>>>
    >>>>>>>it seems to me that nobody needs a high fsb. since they could just
    >>>>>>>push the multiplier really high.
    >>>>>>>
    >>>>>>>I can see the greatness of ddr since the same speed processor can
    >>>>>>>read/write twice as much per cycle. (i assume that the cpu has to be
    >>>>>>>ddr to receive or write double)
    >>>>>>
    >>>>>>How is it you can see the benefit to 'read/write twice as much per cycle'
    >>>>>>yet not see any benefit to more of the cycles?
    >>>>>
    >>>>>
    >>>>>Obviously I see the benefit of more cycles. What do you think I meant
    >>>>>when I said "push the multiplier really high". That increases the
    >>>>>cycles per second.
    >>>>
    >>>>No, increasing the multiplier does NOT increase the FSB cycles.
    >>>
    >>>
    >>>I knew that, it increases cycles per second, but just CPU cycles.
    >>>So yeah. I just realised that:
    >>>Increasing the multiplier increases CPU cycles (not FSB cycles of
    >>>course).
    >>>Increasing the FSB increases both - that is what hadn't occurred to me
    >>>:P
    >>
    >>It isn't because of increasing 'both': that's a matter of the CPU
    >>multiplier being locked, or not.
    >
    >
    > Maybe I wasn't clear with what I meant by both. I didn't mean
    > multiplier and cpu cycles.
    >
    > I meant that increasing the FSB increases both the FSB(naturally!!)
    > and the CPU cycles.

    I knew what you meant.

    >
    > Whilst increasing the multiplier increases only CPU cycles. (the
    > increase in the multiplier only serves the CPU speed. But increasing
    > the FSB serves not just the CPU, but the FSB, which is an integral
    > part of the system)

    Not if you change the multiplier to keep the CPU speed the same. When
    you're looking to what 'effect' something has you keep everything else the
    same so the 'difference', if any, is the result OF that one thing.

    >
    > I think we're in agreement here, as you say
    > "a processor at speed X will perform better if it also has a faster
    > FSB (within reason)."
    > The value of the multiplier only serves to determine the CPU speed.
    > Unlike the FSB. (actrually for a given cpu speed, a higher mnultiplier
    > is worse because it implies a lower fsb)

    'For a given speed' is the point. Yes, a higher FSB, with a lower
    multiplier for the 'same CPU speed', is better. Which was the point of the
    topic "FSB speed - why does it matter?"

    It 'matters' on it's own merit, not simply because it also increases the
    CPU speed and 'CPU speed' is not always in the equation. As in, should I
    buy an XP3200+ 333 FSB or an XP3200+ 400 FSB? Or, my mobile maxes out at
    2400 MHz but, since I can change the multiplier, which FSB would be best:
    266, 333, 400?

    <snip>
  34. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard wrote:
    > Michael Brown wrote:
    >
    >> David Maynard wrote:
    >> [...]
    >>
    >>> The CPU *does* have a 'multiplier'.
    >>
    >>
    >> Oooo, you're lucky you put that in quotes :P
    >
    > It wasn't 'luck'. I use single quotes to denote irony, the 'colloquial
    > gist' (sometimes akin to irony), or non literal use of a word/phrase.
    >
    > In that case I was indicating the colloquial gist of the function and
    > not necessarily a literal.

    Perhaps it's a New Zealand phrase I used ... "You're lucky you did
    [something]" is often used as an equivalent form to "If you hadn't done
    [something] I would have had to do [something else, generally not
    positive]". This doesn't necessarily mean that the person didn't forsee
    [something else] coming and did [something] to avoid [something else]
    happening. In this case the [something else] would have been me upholding my
    role as the technicality nit-picker of the group :)

    [...]

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
  35. Archived from groups: alt.comp.hardware.overclocking (More info?)

    Michael Brown wrote:

    > David Maynard wrote:
    >
    >>Michael Brown wrote:
    >>
    >>
    >>>David Maynard wrote:
    >>>[...]
    >>>
    >>>
    >>>>The CPU *does* have a 'multiplier'.
    >>>
    >>>
    >>>Oooo, you're lucky you put that in quotes :P
    >>
    >>It wasn't 'luck'. I use single quotes to denote irony, the 'colloquial
    >>gist' (sometimes akin to irony), or non literal use of a word/phrase.
    >>
    >>In that case I was indicating the colloquial gist of the function and
    >>not necessarily a literal.
    >
    >
    > Perhaps it's a New Zealand phrase I used ... "You're lucky you did
    > [something]" is often used as an equivalent form to "If you hadn't done
    > [something] I would have had to do [something else, generally not
    > positive]". This doesn't necessarily mean that the person didn't forsee
    > [something else] coming and did [something] to avoid [something else]
    > happening. In this case the [something else] would have been me upholding my
    > role as the technicality nit-picker of the group :)

    :)

    Oh, it means the same thing in the U.S., except there *is* the element of
    'luck' involved whether the casual user realizes it or not, as illustrated
    by the companion phrases that don't (explicitly); such as: "good thing you
    did that, or else..." and "it was wise of you to..." (although both could
    be, and often are, if not usually, used sarcastically to mean 'lucky' anyway).

    They are all intros to the respondent going ahead and dealing with the 'or
    else' regardless of the 'luck', 'goodness', or 'wisdom' of the original
    speaker ;)

    The 'good thing' intro can be easily ignored whereas the 'wise thing' intro
    might elicit a "thank you" but the common reply to a 'lucky' intro is to
    point out it wasn't 'luck', or to admit that it was <g>.

    Your explanation is interesting because I was tempted, but resisted, to say
    "and I did it specifically to avoid nit picking replies; which, obviously,
    didn't work." <g>


    > [...]
    >
    > --
    > Michael Brown
    > www.emboss.co.nz : OOS/RSI software and more :)
    > Add michael@ to emboss.co.nz - My inbox is always open
    >
    >
  36. Archived from groups: alt.comp.hardware.overclocking (More info?)

    David Maynard <dNOTmayn@ev1.net> wrote in message news:<10odr2t1pobgq20@corp.supernews.com>...
    > James Hanley wrote:
    <snip>
    > > David Maynard <dNOTmayn@ev1.net> wrote in message > >
    <snip>
    > > Whilst increasing the multiplier increases only CPU cycles. (the
    > > increase in the multiplier only serves the CPU speed. But increasing
    > > the FSB serves not just the CPU, but the FSB, which is an integral
    > > part of the system)
    >
    > Not if you change the multiplier to keep the CPU speed the same. When
    > you're looking to what 'effect' something has you keep everything else the
    > same so the 'difference', if any, is the result OF that one thing.

    by increasing one thing, like the multiplier, and nothing else, you
    are just seeing the effect of increasing the multiplier. I wouldn't
    call that 'keping everything else the same', I would call it 'me
    changing 1 thing and nothing else', the result, is that many things
    can change. Infact, in the case you mention where you say "if you
    change the multiplier to keep the CPU speed the same" there, you are
    actually changng the multiplier(increasing it) and the fsb(lowering
    it), so you are changing 2 things, that is a bad test. You're
    suggesting chnaging 2 things(fsb and multiplier), by talking about
    changing the multiplier to keep cpu cycles the same. Yet you then
    write of the importance of changing 1 thing only, to see what effect
    it has. I must be misunderstanding your paragraph, but it's not
    important, 'cos I didn't mean changing the multiplier to keep cpu
    cycles the same. I meant changing just the multiplier, thus letting
    cpu cycles rise.


    > >
    > > I think we're in agreement here, as you say
    > > "a processor at speed X will perform better if it also has a faster
    > > FSB (within reason)."
    > > The value of the multiplier only serves to determine the CPU speed.
    > > Unlike the FSB. (actrually for a given cpu speed, a higher mnultiplier
    > > is worse because it implies a lower fsb)
    >
    > 'For a given speed' is the point. Yes, a higher FSB, with a lower
    > multiplier for the 'same CPU speed', is better. Which was the point of the
    > topic "FSB speed - why does it matter?"
    >
    > It 'matters' on it's own merit, not simply because it also increases the
    > CPU speed and 'CPU speed' is not always in the equation. As in, should I
    > buy an XP3200+ 333 FSB or an XP3200+ 400 FSB? Or, my mobile maxes out at
    > 2400 MHz but, since I can change the multiplier, which FSB would be best:
    > 266, 333, 400?
    >
    absolutely.
    (answer to your rhetorical Q is 400)
  37. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    > Infact, in the case you mention where you say "if you change the
    > multiplier to keep the CPU speed the same" there, you are
    > actually changng the multiplier(increasing it) and the fsb(lowering
    > it), so you are changing 2 things, that is a bad test.

    No you're not. You're evaluating the performance difference inherent in
    changing *one* thing (the FSB), because the CPU clock speed stays the same.
    You are missing the point of what David is saying - you need to change *two*
    parameters to measure the effect of *one* change.

    >You're suggesting chnaging 2 things(fsb and multiplier), by talking about
    > changing the multiplier to keep cpu cycles the same. Yet you then
    > write of the importance of changing 1 thing only,

    You're missing the point of changing the CPU multiplier. All it does is
    govern the CPU core frequency. If, for example, you ran a CPU at 100MHz x
    20, or 133.333'MHz x 15, the result would be 2000MHz, and the integer and
    floating point performance of the CPU would be *exactly* the same, allowing
    for any point variations in the PLL. Thus, any changes you saw in benchmark
    performance would be caused by the FSB change.

    > I must be misunderstanding your paragraph,

    You are.

    >I meant changing just the multiplier, thus letting cpu cycles rise.

    This is where your misunderstanding arises. Let's remind you that your
    initial proposal was that FSB isn't, in itself, important. If you tested
    this theory by raising the FSB and leaving the multiplier the same, you
    would see an improvement in CPU integer and floating point performance, and,
    if you didn't change the memory multiplier, you'd see an improvement in
    memory performance too. By changing things like the CPU core and memory bus
    multipliers, you can evaluate the effect of FSB changes without the results
    being clouded by other issues.

    >> which FSB would be best: 266, 333, 400?
    >>
    > absolutely.
    > (answer to your rhetorical Q is 400)

    James, you came into this thread thinking that FSB doesn't matter. The
    answer above indicates that you have revised your opinion. Is this correct?
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  38. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > David Maynard <dNOTmayn@ev1.net> wrote in message news:<10odr2t1pobgq20@corp.supernews.com>...
    >
    >>James Hanley wrote:
    >
    > <snip>
    >
    >>>David Maynard <dNOTmayn@ev1.net> wrote in message > >
    >
    > <snip>
    >
    >>>Whilst increasing the multiplier increases only CPU cycles. (the
    >>>increase in the multiplier only serves the CPU speed. But increasing
    >>>the FSB serves not just the CPU, but the FSB, which is an integral
    >>>part of the system)
    >>
    >>Not if you change the multiplier to keep the CPU speed the same. When
    >>you're looking to what 'effect' something has you keep everything else the
    >>same so the 'difference', if any, is the result OF that one thing.
    >
    >
    > by increasing one thing, like the multiplier, and nothing else, you
    > are just seeing the effect of increasing the multiplier. I wouldn't
    > call that 'keping everything else the same', I would call it 'me
    > changing 1 thing and nothing else', the result, is that many things
    > can change.

    You're being obtuse. Changing, as you call it, the "1 thing" *is* keeping
    everything else 'the same' and observing the effect of changing that "1
    thing."

    How you come up with "many things changing" I don't know but, regardless,
    even if many things 'changed' that *is* the 'effect' of altering the "1
    thing" and observing what changed with everything else remaining the same.

    > Infact, in the case you mention where you say "if you
    > change the multiplier to keep the CPU speed the same" there, you are
    > actually changng the multiplier(increasing it) and the fsb(lowering
    > it), so you are changing 2 things, that is a bad test.

    No, it is the appropriate test if the purpose is to see the effect of the
    FSB itself, and nothing else, on performance. And that was the specific
    point I was trying to convey: that increasing the FSB, alone, improves
    processor performance even at the same processor speed.

    > You're
    > suggesting chnaging 2 things(fsb and multiplier), by talking about
    > changing the multiplier to keep cpu cycles the same. Yet you then
    > write of the importance of changing 1 thing only, to see what effect
    > it has. I must be misunderstanding your paragraph, but it's not
    > important, 'cos I didn't mean changing the multiplier to keep cpu
    > cycles the same. I meant changing just the multiplier, thus letting
    > cpu cycles rise.

    What you misunderstood is the difference between "keeping everything else
    the same" vs what one has to do in order to keep "everything else the same."

    I.E. The effects we want to observe, independent of each other, are the
    results of CPU clock rate and FSB clock rate; not how one 'sets' them.

    >>>I think we're in agreement here, as you say
    >>>"a processor at speed X will perform better if it also has a faster
    >>>FSB (within reason)."
    >>>The value of the multiplier only serves to determine the CPU speed.
    >>>Unlike the FSB. (actrually for a given cpu speed, a higher mnultiplier
    >>>is worse because it implies a lower fsb)
    >>
    >>'For a given speed' is the point. Yes, a higher FSB, with a lower
    >>multiplier for the 'same CPU speed', is better. Which was the point of the
    >>topic "FSB speed - why does it matter?"
    >>
    >>It 'matters' on it's own merit, not simply because it also increases the
    >>CPU speed and 'CPU speed' is not always in the equation. As in, should I
    >>buy an XP3200+ 333 FSB or an XP3200+ 400 FSB? Or, my mobile maxes out at
    >>2400 MHz but, since I can change the multiplier, which FSB would be best:
    >>266, 333, 400?
    >>
    >
    > absolutely.
    > (answer to your rhetorical Q is 400)
  39. Archived from groups: alt.comp.hardware.overclocking (More info?)

    Hi Peps..

    I have a P4 Prescott 560 3.4ghz sockel 775 with a Asus P5ad2 premium
    mainboard. I can unlock my cpu`s multi. in the bios from 18x to 14x. so i
    have a FSB 1066 with cpu speed around 3.7 ghz. it ROCKS. with fsb 800, i
    have cpu speed about 4.2 ghz

    greez
  40. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > it seems to me that nobody needs a high fsb. since they could just
    > push the multiplier really high.
    >
    > I can see the greatness of ddr since the same speed processor can
    > read/write twice as much per cycle. (i assume that the cpu has to be
    > ddr to receive or write double)

    Here's a real example of why FSB matters ;-)

    I have a pair of Tualatin-S engineering samples, (no multiplier lock),
    and a modified dual processor motherboard (Asus P2B-DS), so I can
    benchmark the processors at various FSB and multiplier settings which
    result in (close to) the same CPU clock speed. PCmark2002 results:

    CPU Mhz FSB Multi CPU Test RAM Test
    950 100 9.5 3044 1711
    931 133 7 3019 1948
    910 140 6.5 2960 2010

    Clearly RAM performance improves as FSB is increased, while CPU
    performance remains proportional to CPU clock speed.

    More detailed results here:

    http://tipperlinne.com/benchmark.htm

    P2B
  41. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Richard Hopkins" <richh@dsl.nospam.co.uk> wrote in message news:<4187e473$0$1397$cc9e4d1f@news-text.dial.pipex.com>...
    > "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message
    > > Infact, in the case you mention where you say "if you change the
    > > multiplier to keep the CPU speed the same" there, you are
    > > actually changng the multiplier(increasing it) and the fsb(lowering
    > > it), so you are changing 2 things, that is a bad test.
    >
    > No you're not. You're evaluating the performance difference inherent in
    > changing *one* thing (the FSB), because the CPU clock speed stays the same.
    > You are missing the point of what David is saying - you need to change *two*
    > parameters to measure the effect of *one* change.
    >
    > >You're suggesting chnaging 2 things(fsb and multiplier), by talking about
    > > changing the multiplier to keep cpu cycles the same. Yet you then
    > > write of the importance of changing 1 thing only,
    >
    > You're missing the point of changing the CPU multiplier. All it does is
    > govern the CPU core frequency. If, for example, you ran a CPU at 100MHz x
    > 20, or 133.333'MHz x 15, the result would be 2000MHz, and the integer and
    > floating point performance of the CPU would be *exactly* the same, allowing
    > for any point variations in the PLL. Thus, any changes you saw in benchmark
    > performance would be caused by the FSB change.
    >
    > > I must be misunderstanding your paragraph,
    >
    > You are.

    Thanks, I understand it now, I see what David meant when he said my
    test was a bad one. Though my example wasn't a test to prove anything,
    it was just an exmaple where an increase in FSB improves system
    performance for the 2 reasons. It definitely didn't prove anything.
    If it were a test it would have been a bad one. I can now see where
    David was coming from. I can see the benefits of david's test over my
    example, since he proves that an FSB increase improves system
    performance purely because the system has a faster FSB.


    > >I meant changing just the multiplier, thus letting cpu cycles rise.
    >
    > This is where your misunderstanding arises. Let's remind you that your
    > initial proposal was that FSB isn't, in itself, important. If you tested
    > this theory by raising the FSB and leaving the multiplier the same, you
    > would see an improvement in CPU integer and floating point performance, and,
    > if you didn't change the memory multiplier, you'd see an improvement in
    > memory performance too. By changing things like the CPU core and memory bus
    > multipliers, you can evaluate the effect of FSB changes without the results
    > being clouded by other issues.

    right, thanks

    > >> which FSB would be best: 266, 333, 400?
    > >>
    > > absolutely.
    > > (answer to your rhetorical Q is 400)
    >
    > James, you came into this thread thinking that FSB doesn't matter. The
    > answer above indicates that you have revised your opinion. Is this correct?

    yes.

    note- I stated earlier in the thread that I had revised my opinion -
    that I was wrong before.


    thanks.
  42. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Richard Hopkins" <richh@dsl.nospam.co.uk> wrote in message news:<41861725$0$755$cc9e4d1f@news-text.dial.pipex.com>...
    > "James Hanley" <jameshanley39@yahoo.co.uk> wrote in message ...
    > > memory frequency can be increased to a multiple of the FSB even
    > > before DDR is 'applied'.
    >
    > Of course it can. Trouble is that you can do what the hell you like to the
    > FSB:memory multiplier, but after a certain point the connection between the
    > memory and the processor can't keep up, so your increases in memory speed
    > are wasted. What is the point of having, say, 8GB/sec memory bandwidth if
    > the link between the memory controller and the CPU only runs at 4GB/sec?

    I agree, but
    what seems strange is an increase in bandwidth via- Dual inline
    memory. doubling the bandwidth of the memory bus. Well, as far as I
    understand it, the FSB and Memory bus are connected, and often
    considered as one bus connecting cpu to memory. The FSB seems to be
    the end towards the processor, and the memory bus seems to be the end
    towards memeory. (i'm aware that the athlon 64 has no fsb / gives a
    different name to the bus between cpu and memory) So Dual inline
    memory presumably doubles the bandwidth of the memory bus and fsb. So
    it must be a special FSB/Memory bus that doubles in bandwidth for
    when memory reads or writes (but not for the cpu reading and
    writing!).
    Here's the weird bit that seems very strange though. Dual inline
    memory is not considered to increase the effective speed. Yet in each
    cycle, the memory can r/w twice as much. So that means that the cpu
    and memory cannot be efficiently synchronized when the cpu's access to
    the FSB and the memory's access to the memory bus are at the same
    effective speed. They are only efficiently syhcnronized when the cpu
    is accessing the FSB at twice the speed that the memory is accessing
    the memory bus / when the memory's effective speed is half that at
    which the cpu accesses the fsb. To put it another way, only with the
    dual inline memory accessing the fsb at half the effective speed that
    the cpu accesses the fsb, would the bandwidth be equal, and memory
    cycles go unwasted.

    > > I have an option in my BIOS to set my DDR-SDRAM frequency,
    > > I can set my FSB to 100 and my SDRAM to 266 (effective).
    >
    > Virtually all motherboards do this nowadays. However, you are better off
    > keeping a synchronous memory bus and raising the FSB than you are clocking
    > the memory bus up and leaving the FSB slower. In both AMD (HyperTransport)
    > and Intel (NetBurst Bus) cases, the FSB directly controls the speed of the
    > internal processor to memory bus, and only by keeping the bandwidth of this
    > bus at least equal to the memory bandwidth can you take full advantage of
    > the memory speed.
    >
    > This is why both AMD and Intel have been raising the effective FSB of their
    > motherboards and processors the last few years. Look at the way Intel went
    > from 100 (effective 400MHz QDR) FSB to (soon) 266MHz (effectively 1066MHz).
    > The reason they've done it is to allow sufficient headroom for ever faster
    > memory to interface optimally with the processor.
    >
    > > So both RAM and CPU can operate at a frequency that is a multiple of
    > > the FSB.
    > > So memory frequency can be increased without increasing the FSB.
    >
    > Of course it can. The processor bus speed, by contrast, can only be
    > increased by increasing the FSB.
    >
    > > (i'm assuming bandwidth=throughput, but I cannot check at this moment,
    > > since I'm leaving in a minute, so I have to click Send now!!
    >
    > For the purposes of this conversation, bandwidth does equal throughput.
    > --
    thanks
  43. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" wrote in message...
    > I agree, but
    > what seems strange is an increase in bandwidth via- Dual inline
    > memory. doubling the bandwidth of the memory bus.

    What's strange about that?

    > Well, as far as I understand it, the FSB and Memory bus are connected,

    They're connected, yes. Either synchronously or asynchronously, via a series
    of multipliers/dividers. They don't *have* to be connected though. In theory
    it's possible to run the two buses on separate PLL's, it's just more
    practical to run them, as well as other timing critical items from a single
    timebase.

    > and often considered as one bus connecting cpu to memory.

    To be strictly accurate, they're two, closely interlinked buses, one between
    CPU and memory controller, and the other between memory controller and
    memory. Even though, in practice, these two buses are normally run off the
    same clock generator, don't assume that they're the same thing, although
    admittedly the dividing lines between the two are becoming more blurred all
    the time. The AMD Socket 939 chips have their memory controller onboard the
    CPU for example - shortening the physical connections, and thus boosting
    performance.

    > Also, The FSB seems to be the end towards the processor, and
    > the memory bus seems to be the end towards memeory.

    Your terminology's not quite right, but you do generally have the right
    idea.

    > (i'm aware that the athlon 64 has no fsb / gives a different
    > name to the bus between cpu and memory)

    The theory's the same, even though, as you say, the nomenclature is
    different and the geography, as mentioned above, is quite confusing.

    > So Dual inline memory presumably doubles the bandwidth of the
    > memory bus and fsb.

    No. A dual channel memory controller doubles the *width* of the memory bus,
    effectively reading from/writing to two banks of memory in parallel. It
    doesn't, in itself have any effect on the speed or bandwidth of the front
    side bus.

    > So it must be a special FSB/Memory bus that doubles in
    > bandwidth for when memory reads or writes

    You already know about the effect double data rate and quad data rate buses
    have on bandwidth, so the rest should be pretty simple. You have to grasp
    the difference between speed (i.e. clock cycles per second), width (number
    of bytes written/read per cycle) and bandwidth (clocks per second multiplied
    by width multiplied by the number of data transfers per clock).
    An eight bit wide single data rate interface running at 1Hz has a bandwidth
    of eight bits per second. A sixteen bit wide interface running at 1Hz has a
    bandwidth of 16bps, and an eight bit wide interface running at 1Hz with two
    accesses per clock (i.e DDR) also has a bandwidth of 16bps. All three
    parameters - speed, width and data rate contribute to the overall bandwidth
    of a digital connection.

    > Here's the weird bit that seems very strange though. Dual
    > inline memory is not considered to increase the effective
    > speed.

    It doesn't increase the speed in cycles per second, but doubles the
    effective width of the memory interface. Remember that bandwidth=width x
    speed, so if the speed stays the same but the width doubles, the bandwidth
    also doubles.

    > Yet in each cycle, the memory can r/w twice as much. So that
    > means that the cpu and memory cannot be efficiently synchronized

    Yes they can, it all depends on the geometry of the processor bus

    > when the cpu's access to the FSB and the memory's access to the
    > memory bus are at the same effective speed. They are only efficiently
    > syhcnronized when the cpu is accessing the FSB at twice the speed
    > that the memory is accessing the memory bus

    No, that's wrong. You're ass-u-ming that the geometry of the processor and
    memory buses are the same. In most cases they're not.

    > To put it another way, only with the dual inline memory accessing
    > the fsb at half the effective speed that the cpu accesses the fsb,
    > would the bandwidth be equal, and memory cycles go unwasted.

    Depending on what platform you are talking about, that's wrong. Take the
    Pentium 4 as an example:

    The bus between the memory controller and the processor is 8 bytes wide and
    runs on a quad data rate cycle. At 200MHz FSB, that gives you an effective
    800MHz bus, which, multiplied by 8 bytes, gives you an overall bandwidth of
    6.4GB/sec.

    The 800MHz Pentium 4's are designed to use PC3200 memory in a dual channel
    configuration.

    Each DDR-SDRAM interface is 64 bits wide, so in a dual channel configuration
    you effectively have a 128 bit wide memory bus. PC3200 runs at a 200MHz base
    clock, with a double data rate cycle. Multiply all this together, and you
    get - surprise surprise, 6.4GB/sec. As you can see, in this instance the
    bandwidth of the processor bus, and the bandwidth of the memory bus, is
    equal.

    If you take the evolution of the Pentium 4 as an example, you can also see
    why FSB *is* important when it comes to raising the performance of a fixed
    architecture. The original P4's had a 400MHz QDR FSB, giving the processor
    bus a bandwidth of 3.2GB/sec. This was designed to mate with PC800 Rambus
    memory in a dual channel configuration, which also ran at 3.2GB/sec.

    When the first single channel DDR P4 chipsets were introduced, memory
    bandwidth actually lagged behind the processor for a while - when 533MHz FSB
    P4's (4.2GB/sec processor bus) were being run with a single channel of
    PC2700 (<2.7GB/sec).

    Continuing the P4 example, you can see why your original "FSB doesn't
    matter" comment caused the reaction it did.

    If, for example, you managed to build a system with, say, one of the
    original Pentium 4 2.4MHz 400FSB parts and dual channel PC3200 memory
    running on a 2:1 multiplier, you'd have 6.4GB/sec of memory bandwidth on
    tap, but a processor bus that only ran at 3.2GB/sec.

    If, on the other hand, you substituted a Pentium 4 2.4C, 800MHz FSB chip
    (with Hyperthreading disabled) and synchronised the processor and memory
    buses, the performance of the system would leap, even though the processor
    itself was running at the same speed.

    You can also now see why raising the FSB is the most effective way to
    increase overall system performance. If you raise the FSB by 33%, you not
    only raise the CPU core clock 33%, you raise the bandwidth of the processor
    bus by 33% too. If you keep your memory synchronous, you also raise the
    bandwidth of the memory bus by 33%. The overall effect will be, there or
    thereabouts, a 33% improvement in performance.

    If, OTOH, you keep the FSB the same, but raise the CPU and memory
    multipliers by 33%, you get the faster memory and CPU clocks, but you don't
    raise the processor bus, so the resulting bottleneck - assuming that the
    bandwidths matched in the first place - will curtail your performance gain.

    Make sense now?
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  44. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" wrote in message...
    > I agree, but
    > what seems strange is an increase in bandwidth via- Dual inline
    > memory. doubling the bandwidth of the memory bus.

    What's strange about that?

    > Well, as far as I understand it, the FSB and Memory bus are connected,

    They're connected, yes. Either synchronously or asynchronously, via a series
    of multipliers/dividers. They don't *have* to be connected though. In theory
    it's possible to run the two buses on separate PLL's, it's just more
    practical to run them, as well as other timing critical items from a single
    timebase.

    > and often considered as one bus connecting cpu to memory.

    To be strictly accurate, they're two, closely interlinked buses, one between
    CPU and memory controller, and the other between memory controller and
    memory. Even though, in practice, these two buses are normally run off the
    same clock generator, don't assume that they're the same thing, although
    admittedly the dividing lines between the two are becoming more blurred all
    the time. The AMD Socket 939 chips have their memory controller onboard the
    CPU for example - shortening the physical connections, and thus boosting
    performance.

    > Also, The FSB seems to be the end towards the processor, and
    > the memory bus seems to be the end towards memeory.

    Your terminology's not quite right, but you do generally have the right
    idea.

    > (i'm aware that the athlon 64 has no fsb / gives a different
    > name to the bus between cpu and memory)

    The theory's the same, even though, as you say, the nomenclature is
    different and the geography, as mentioned above, is quite confusing.

    > So Dual inline memory presumably doubles the bandwidth of the
    > memory bus and fsb.

    No. A dual channel memory controller doubles the *width* of the memory bus,
    effectively reading from/writing to two banks of memory in parallel. It
    doesn't, in itself have any effect on the speed or bandwidth of the front
    side bus.

    > So it must be a special FSB/Memory bus that doubles in
    > bandwidth for when memory reads or writes

    You already know about the effect double data rate and quad data rate buses
    have on bandwidth, so the rest should be pretty simple. You have to grasp
    the difference between speed (i.e. clock cycles per second), width (number
    of bytes written/read per cycle) and bandwidth (clocks per second multiplied
    by width multiplied by the number of data transfers per clock).
    An eight bit wide single data rate interface running at 1Hz has a bandwidth
    of eight bits per second. A sixteen bit wide interface running at 1Hz has a
    bandwidth of 16bps, and an eight bit wide interface running at 1Hz with two
    accesses per clock (i.e DDR) also has a bandwidth of 16bps. All three
    parameters - speed, width and data rate contribute to the overall bandwidth
    of a digital connection.

    > Here's the weird bit that seems very strange though. Dual
    > inline memory is not considered to increase the effective
    > speed.

    It doesn't increase the speed in cycles per second, but doubles the
    effective width of the memory interface. Remember that bandwidth=width x
    speed, so if the speed stays the same but the width doubles, the bandwidth
    also doubles.

    > Yet in each cycle, the memory can r/w twice as much. So that
    > means that the cpu and memory cannot be efficiently synchronized

    Yes they can, it all depends on the geometry of the processor bus

    > when the cpu's access to the FSB and the memory's access to the
    > memory bus are at the same effective speed. They are only efficiently
    > syhcnronized when the cpu is accessing the FSB at twice the speed
    > that the memory is accessing the memory bus

    No, that's wrong. You're ass-u-ming that the geometry of the processor and
    memory buses are the same. In most cases they're not.

    > To put it another way, only with the dual inline memory accessing
    > the fsb at half the effective speed that the cpu accesses the fsb,
    > would the bandwidth be equal, and memory cycles go unwasted.

    Depending on what platform you are talking about, that's wrong. Take the
    Pentium 4 as an example:

    The bus between the memory controller and the processor is 8 bytes wide and
    runs on a quad data rate cycle. At 200MHz FSB, that gives you an effective
    800MHz bus, which, multiplied by 8 bytes, gives you an overall bandwidth of
    6.4GB/sec.

    The 800MHz Pentium 4's are designed to use PC3200 memory in a dual channel
    configuration.

    Each DDR-SDRAM interface is 64 bits wide, so in a dual channel configuration
    you effectively have a 128 bit wide memory bus. PC3200 runs at a 200MHz base
    clock, with a double data rate cycle. Multiply all this together, and you
    get - surprise surprise, 6.4GB/sec. As you can see, in this instance the
    bandwidth of the processor bus, and the bandwidth of the memory bus, is
    equal.

    If you take the evolution of the Pentium 4 as an example, you can also see
    why FSB *is* important when it comes to raising the performance of a fixed
    architecture. The original P4's had a 400MHz QDR FSB, giving the processor
    bus a bandwidth of 3.2GB/sec. This was designed to mate with PC800 Rambus
    memory in a dual channel configuration, which also ran at 3.2GB/sec.

    When the first single channel DDR P4 chipsets were introduced, memory
    bandwidth actually lagged behind the processor for a while - when 533MHz FSB
    P4's (4.2GB/sec processor bus) were being run with a single channel of
    PC2700 (<2.7GB/sec).

    Continuing the P4 example, you can see why your original "FSB doesn't
    matter" comment caused the reaction it did.

    If, for example, you managed to build a system with, say, one of the
    original Pentium 4 2.4MHz 400FSB parts and dual channel PC3200 memory
    running on a 2:1 multiplier, you'd have 6.4GB/sec of memory bandwidth on
    tap, but a processor bus that only ran at 3.2GB/sec.

    If, on the other hand, you substituted a Pentium 4 2.4C, 800MHz FSB chip
    (with Hyperthreading disabled) and synchronised the processor and memory
    buses, the overall performance of the system would leap, even though the
    processor and memory were running at exactly the same speed.

    You can also now see why raising the FSB is the most effective way to
    increase overall system performance given a fixed architecture. If you raise
    the FSB by 33%, you not only raise the CPU core clock 33%, you raise the
    bandwidth of the processor bus by 33% too. If you keep your memory
    synchronous, you also raise the bandwidth of the memory bus by 33%. The
    overall effect will be, in pure number crunching terms, and forgetting about
    all other issues, a 33% improvement.

    If, OTOH, you keep the FSB the same, but raise the CPU and memory
    buses 33% by means of altered multipliers, you get the faster memory and CPU
    clocks, but you don't raise the processor bus, so the resulting bottleneck -
    assuming that the bandwidths matched in the first place - will greatly
    curtail your performance gain. If the data can't flow between the memory and
    CPU fast enough, the CPU sits there twiddling its thumbs rather than
    processing data.

    Make sense now?
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  45. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "Richard Hopkins" <richh@dsl.nospam.co.uk> wrote in message news:<4189c218$0$16437$cc9e4d1f@news-text.dial.pipex.com>...
    > "James Hanley" wrote in message...

    <snip my errant thinking which you corrected where I thought that the
    fsb and memory bus were to be considered parts of the same bus, and
    where i was puzzled as to whether the fsb effectively doubled in width
    with dual inline memory!!
    I understand your response, about the fsb, memory bus, cpu and memory
    cobtroller. >


    > > Here's the weird bit that seems very strange though. Dual
    > > inline memory is not considered to increase the effective
    > > speed.
    >
    > It doesn't increase the speed in cycles per second, but doubles the
    > effective width of the memory interface. Remember that bandwidth=width x
    > speed, so if the speed stays the same but the width doubles, the bandwidth
    > also doubles.

    well. Course Neither Dual inline nor DDR increase the actual speed.
    However, DDR is considered to increase the effective speed, even
    though it does not increase the speed in cycles per second. It just
    writes twice as much per cycle, which has the same effect as working
    at twice the frequency. Similarly, I would have expected Dual inline
    to increase the ‘effective speed' even though – like DDR, it doesn't
    increase the actual speed in cycles per second. It writes twice as
    much – just not on the same wires/conductors, but on a new/unused set.

    > > Yet in each cycle, the memory can r/w twice as much. So that
    > > means that the cpu and memory cannot be efficiently synchronized
    >
    > Yes they can, it all depends on the geometry of the processor bus

    according to the table in pcguide.com article "Memory Banks and
    Package Bit Width", it says Pentiums have a 64-bit data bus. In Scott
    mueller's article formally on upgraingandrepairingpcs.com, now on
    quepublishing.com, titled "Understanding PC2700 (DDR333) and PC3200
    (DDR400) Memory" there's a table that says that DDR RAM from PC66 to
    PC4300 have a 64-bit bus.
    So a Pentium with DDR RAM DIMMS has a 64-bit data bus and 64-bit
    memory bus. If the effective speeds are the same, - for example – the
    actual FSB is the same, the FSB is dual pumped and so is the memory
    bus, so the effective speeds are the same. Therefore if a pair of
    memory modules are used, then the memory bus would ‘effectively' be
    128-bit, hence doubling the bandwidth, but would be said to be running
    at the same effective speed as it was when it was 64-bit. If the
    memory bus can throw around twice as much data as the FSB, then it is
    not an efficient set up. It is only efficient if the DDR RAM is half
    the speed of the FSB. Since in one memory bus clock cycle when
    reading, there are 2 servings for the FSB, it would require 2 FSB
    cycles to pick up the data. Similarly when writing.


    > > when the cpu's access to the FSB and the memory's access to the
    > > memory bus are at the same effective speed. They are only efficiently
    > > syhcnronized when the cpu is accessing the FSB at twice the speed
    > > that the memory is accessing the memory bus
    >
    > No, that's wrong. You're ass-u-ming that the geometry of the processor and
    > memory buses are the same. In most cases they're not.

    yeah, I was assuming that, but based on the tables I saw at
    pcguide.com and scott mueller's article. Collectively they said that
    Pentiums have 64-bit data buses and DDR RAM (at least PC66-PC4300) has
    64-bit memory bus.
    To me, that means that the geometry is the same.


    >
    > > To put it another way, only with the dual inline memory accessing
    > > the fsb at half the effective speed that the cpu accesses the fsb,
    > > would the bandwidth be equal, and memory cycles go unwasted.
    >
    > Depending on what platform you are talking about, that's wrong. Take the
    > Pentium 4 as an example:
    >
    > The bus between the memory controller and the processor is 8 bytes wide and
    > runs on a quad data rate cycle. At 200MHz FSB, that gives you an effective
    > 800MHz bus, which, multiplied by 8 bytes, gives you an overall bandwidth of
    > 6.4GB/sec.
    >
    > The 800MHz Pentium 4's are designed to use PC3200 memory in a dual channel
    > configuration.
    >
    > Each DDR-SDRAM interface is 64 bits wide, so in a dual channel configuration
    > you effectively have a 128 bit wide memory bus. PC3200 runs at a 200MHz base
    > clock, with a double data rate cycle. Multiply all this together, and you
    > get - surprise surprise, 6.4GB/sec. As you can see, in this instance the
    > bandwidth of the processor bus, and the bandwidth of the memory bus, is
    > equal.

    but isn't that a beautiful real world illustration of what I mean. In
    that example, the effective speed of the FSB is 800=4*200. And the
    effective speed of the memory bus is 400=2*200. It's efficient,
    because the bandwidth is equal. Although that required the actual
    speeds to be the same, it means that the FSB's effective speed is
    half that of the memory bus.

    > If you take the evolution of the Pentium 4 as an example, you can also see
    > why FSB *is* important when it comes to raising the performance of a fixed
    > architecture. The original P4's had a 400MHz QDR FSB, giving the processor
    > bus a bandwidth of 3.2GB/sec. This was designed to mate with PC800 Rambus
    > memory in a dual channel configuration, which also ran at 3.2GB/sec.
    >
    > When the first single channel DDR P4 chipsets were introduced, memory
    > bandwidth actually lagged behind the processor for a while - when 533MHz FSB
    > P4's (4.2GB/sec processor bus) were being run with a single channel of
    > PC2700 (<2.7GB/sec).
    >
    > Continuing the P4 example, you can see why your original "FSB doesn't
    > matter" comment caused the reaction it did.

    yeah

    > If, for example, you managed to build a system with, say, one of the
    > original Pentium 4 2.4MHz 400FSB parts and dual channel PC3200 memory
    > running on a 2:1 multiplier, you'd have 6.4GB/sec of memory bandwidth on
    > tap, but a processor bus that only ran at 3.2GB/sec.
    >
    > If, on the other hand, you substituted a Pentium 4 2.4C, 800MHz FSB chip
    > (with Hyperthreading disabled) and synchronised the processor and memory
    > buses, the performance of the system would leap, even though the processor
    > itself was running at the same speed.
    >
    > You can also now see why raising the FSB is the most effective way to
    > increase overall system performance. If you raise the FSB by 33%, you not
    > only raise the CPU core clock 33%, you raise the bandwidth of the processor
    > bus by 33% too. If you keep your memory synchronous, you also raise the
    > bandwidth of the memory bus by 33%. The overall effect will be, there or
    > thereabouts, a 33% improvement in performance.

    Lemme see!
    P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) – a 2:1
    multiplier.
    That system, as you explained, has the bandwidths equal, because it's
    dual inline.

    FSB actual speed upped by 33% puts it from 200MHz to 266MHz.
    Effective FSB speed (quad pumped) = 1066MHz(266*4)
    FSB Bandwidth= 1066MHz * 8 = 8.5GB/s

    DDR-SDRAM actual speed = 200MHz upped by 33% naturally = 266MHz
    Effective DDR-SDRAM speed = 266*2 = 533MHz
    Memory bus bandwidth before dual inline is applied = 4.2GB/s
    Memory bus bandwidth after dual inline is applied = 8.5GB/s

    I understand you there then. Yeah,
    I can see. 200*4*8=200*2*8*2 ;)

    When you say "If you keep your memory synchronous, you also raise the
    bandwidth of the memory bus by 33%." You mean keeping the actual
    memory speed equal to the processor speed, right? The word
    synchronous is a funny one to use, because SDRAM is always
    synchronous, that's what the S stands for. If the actual speeds are
    different, it would stiull be synchronous, and if the multiplier were
    non-integer, it would be pseudo-synchronous / pseudo-sync, which is
    still synchronized, but I've read that via may call it async for some
    reason. There was a long thread on the subject of pseudo-sync and
    related issues such as async mode, in comp.sys.ibm.pc.hardware.chips
    in sept 2004.


    > If, OTOH, you keep the FSB the same, but raise the CPU and memory
    > multipliers by 33%, you get the faster memory and CPU clocks, but you don't
    > raise the processor bus, so the resulting bottleneck - assuming that the
    > bandwidths matched in the first place - will curtail your performance gain.

    And in your earlier example
    P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) – a 2:1
    multiplier.
    There's no bottleneck because the bandwidths of the fsb and memory bus
    are equal. (effective speeds being different and actual speeds being
    the same, are irrelevant).


    > Make sense now?


    yeah, and those calculations i did with the 33% increase all agree
    with what you're saying.

    thanks
  46. Archived from groups: alt.comp.hardware.overclocking (More info?)

    google groups seems to be be a bit slow in posting and archiving ,
    i'll post this again. Maybe the other earlier post didn't get through.
    My ISP seem to be unable to provide a working news server.

    "Richard Hopkins" <richh@dsl.nospam.co.uk> wrote in message news:<4189c218$0$16437$cc9e4d1f@news-text.dial.pipex.com>...
    > "James Hanley" wrote in message...

    <snip my errant thinking which you corrected where I thought that the
    fsb and memory bus were to be considered parts of the same bus, and
    where i was puzzled as to whether the fsb effectively doubled in width
    with dual inline memory!!
    I understand your response, about the fsb, memory bus, cpu and memory
    cobtroller. >


    > > Here's the weird bit that seems very strange though. Dual
    > > inline memory is not considered to increase the effective
    > > speed.
    >
    > It doesn't increase the speed in cycles per second, but doubles the
    > effective width of the memory interface. Remember that bandwidth=width x
    > speed, so if the speed stays the same but the width doubles, the bandwidth
    > also doubles.

    well. Course Neither Dual inline nor DDR increase the actual speed.
    However, DDR is considered to increase the effective speed, even
    though it does not increase the speed in cycles per second. It just
    writes twice as much per cycle, which has the same effect as working
    at twice the frequency. Similarly, I would have expected Dual inline
    to increase the ‘effective speed' even though – like DDR, it doesn't
    increase the actual speed in cycles per second. It writes twice as
    much – just not on the same wires/conductors, but on a new/unused set.

    > > Yet in each cycle, the memory can r/w twice as much. So that
    > > means that the cpu and memory cannot be efficiently synchronized
    >
    > Yes they can, it all depends on the geometry of the processor bus

    according to the table in pcguide.com article "Memory Banks and
    Package Bit Width", it says Pentiums have a 64-bit data bus. In Scott
    mueller's article formally on upgraingandrepairingpcs.com, now on
    quepublishing.com, titled "Understanding PC2700 (DDR333) and PC3200
    (DDR400) Memory" there's a table that says that DDR RAM from PC66 to
    PC4300 have a 64-bit bus.
    So a Pentium with DDR RAM DIMMS has a 64-bit data bus and 64-bit
    memory bus. If the effective speeds are the same, - for example – the
    actual FSB is the same, the FSB is dual pumped and so is the memory
    bus, so the effective speeds are the same. Therefore if a pair of
    memory modules are used, then the memory bus would ‘effectively' be
    128-bit, hence doubling the bandwidth, but would be said to be running
    at the same effective speed as it was when it was 64-bit. If the
    memory bus can throw around twice as much data as the FSB, then it is
    not an efficient set up. It is only efficient if the DDR RAM is half
    the speed of the FSB. Since in one memory bus clock cycle when
    reading, there are 2 servings for the FSB, it would require 2 FSB
    cycles to pick up the data. Similarly when writing.


    > > when the cpu's access to the FSB and the memory's access to the
    > > memory bus are at the same effective speed. They are only efficiently
    > > syhcnronized when the cpu is accessing the FSB at twice the speed
    > > that the memory is accessing the memory bus
    >
    > No, that's wrong. You're ass-u-ming that the geometry of the processor and
    > memory buses are the same. In most cases they're not.

    yeah, I was assuming that, but based on the tables I saw at
    pcguide.com and scott mueller's article. Collectively they said that
    Pentiums have 64-bit data buses and DDR RAM (at least PC66-PC4300) has
    64-bit memory bus.
    To me, that means that the geometry is the same.


    >
    > > To put it another way, only with the dual inline memory accessing
    > > the fsb at half the effective speed that the cpu accesses the fsb,
    > > would the bandwidth be equal, and memory cycles go unwasted.
    >
    > Depending on what platform you are talking about, that's wrong. Take the
    > Pentium 4 as an example:
    >
    > The bus between the memory controller and the processor is 8 bytes wide and
    > runs on a quad data rate cycle. At 200MHz FSB, that gives you an effective
    > 800MHz bus, which, multiplied by 8 bytes, gives you an overall bandwidth of
    > 6.4GB/sec.
    >
    > The 800MHz Pentium 4's are designed to use PC3200 memory in a dual channel
    > configuration.
    >
    > Each DDR-SDRAM interface is 64 bits wide, so in a dual channel configuration
    > you effectively have a 128 bit wide memory bus. PC3200 runs at a 200MHz base
    > clock, with a double data rate cycle. Multiply all this together, and you
    > get - surprise surprise, 6.4GB/sec. As you can see, in this instance the
    > bandwidth of the processor bus, and the bandwidth of the memory bus, is
    > equal.

    but isn't that a beautiful real world illustration of what I mean. In
    that example, the effective speed of the FSB is 800=4*200. And the
    effective speed of the memory bus is 400=2*200. It's efficient,
    because the bandwidth is equal. Although that required the actual
    speeds to be the same, it means that the FSB's effective speed is
    half that of the memory bus.

    > If you take the evolution of the Pentium 4 as an example, you can also see
    > why FSB *is* important when it comes to raising the performance of a fixed
    > architecture. The original P4's had a 400MHz QDR FSB, giving the processor
    > bus a bandwidth of 3.2GB/sec. This was designed to mate with PC800 Rambus
    > memory in a dual channel configuration, which also ran at 3.2GB/sec.
    >
    > When the first single channel DDR P4 chipsets were introduced, memory
    > bandwidth actually lagged behind the processor for a while - when 533MHz FSB
    > P4's (4.2GB/sec processor bus) were being run with a single channel of
    > PC2700 (<2.7GB/sec).
    >
    > Continuing the P4 example, you can see why your original "FSB doesn't
    > matter" comment caused the reaction it did.

    yeah

    > If, for example, you managed to build a system with, say, one of the
    > original Pentium 4 2.4MHz 400FSB parts and dual channel PC3200 memory
    > running on a 2:1 multiplier, you'd have 6.4GB/sec of memory bandwidth on
    > tap, but a processor bus that only ran at 3.2GB/sec.
    >
    > If, on the other hand, you substituted a Pentium 4 2.4C, 800MHz FSB chip
    > (with Hyperthreading disabled) and synchronised the processor and memory
    > buses, the performance of the system would leap, even though the processor
    > itself was running at the same speed.
    >
    > You can also now see why raising the FSB is the most effective way to
    > increase overall system performance. If you raise the FSB by 33%, you not
    > only raise the CPU core clock 33%, you raise the bandwidth of the processor
    > bus by 33% too. If you keep your memory synchronous, you also raise the
    > bandwidth of the memory bus by 33%. The overall effect will be, there or
    > thereabouts, a 33% improvement in performance.

    Lemme see!
    P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) – a 2:1
    multiplier.
    That system, as you explained, has the bandwidths equal, because it's
    dual inline.

    FSB actual speed upped by 33% puts it from 200MHz to 266MHz.
    Effective FSB speed (quad pumped) = 1066MHz(266*4)
    FSB Bandwidth= 1066MHz * 8 = 8.5GB/s

    DDR-SDRAM actual speed = 200MHz upped by 33% naturally = 266MHz
    Effective DDR-SDRAM speed = 266*2 = 533MHz
    Memory bus bandwidth before dual inline is applied = 4.2GB/s
    Memory bus bandwidth after dual inline is applied = 8.5GB/s

    I understand you there then. Yeah,
    I can see. 200*4*8=200*2*8*2 ;)

    When you say "If you keep your memory synchronous, you also raise the
    bandwidth of the memory bus by 33%." You mean keeping the actual
    memory speed equal to the processor speed, right? The word
    synchronous is a funny one to use, because SDRAM is always
    synchronous, that's what the S stands for. If the actual speeds are
    different, it would stiull be synchronous, and if the multiplier were
    non-integer, it would be pseudo-synchronous / pseudo-sync, which is
    still synchronized, but I've read that via may call it async for some
    reason. There was a long thread on the subject of pseudo-sync and
    related issues such as async mode, in comp.sys.ibm.pc.hardware.chips
    in sept 2004.


    > If, OTOH, you keep the FSB the same, but raise the CPU and memory
    > multipliers by 33%, you get the faster memory and CPU clocks, but you don't
    > raise the processor bus, so the resulting bottleneck - assuming that the
    > bandwidths matched in the first place - will curtail your performance gain.

    And in your earlier example
    P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) – a 2:1
    multiplier.
    There's no bottleneck because the bandwidths of the fsb and memory bus
    are equal. (effective speeds being different and actual speeds being
    the same, are irrelevant).


    > Make sense now?


    yeah, and those calculations i did with the 33% increase all agree
    with what you're saying.

    thanks
  47. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" wrote in message...
    > Course Neither Dual inline nor DDR increase the actual speed.

    You have to be careful with your terminology here, as you're in danger of
    confusing/transposing different factors. In particular it looks like you're
    a little too keen to mix bus speeds and bandwidths.

    > However, DDR is considered to increase the effective speed, even
    > though it does not increase the speed in cycles per second.

    Double data rate increases bandwidth, not speed. ;-)

    > It just writes twice as much per cycle, which has the same effect
    > as working at twice the frequency.

    Correct.

    > according to the table in pcguide.com article "Memory Banks
    > and Package Bit Width", it says Pentiums have a 64-bit data
    > bus.

    Yes, eight bytes/64 bits. I mentioned this in my previous post.

    > So a Pentium with DDR RAM DIMMS has a 64-bit data bus and
    > 64-bit memory bus. If the effective speeds are the same, - for
    > example - the actual FSB is the same, the FSB is dual pumped
    > and so is the memory bus,

    No. The front side bus on the Pentium 4 CPU's is *quad* pumped, so four data
    transfers per clock, not two as you say above.

    > If the memory bus can throw around twice as much data as the
    > FSB, then it is not an efficient set up.

    That comment is incorrect, because your underlying assumption about the P4
    processor bus being double pumped is wrong.

    > It is only efficient if the DDR RAM is half the speed of the FSB.

    See above.

    > Since in one memory bus clock cycle when reading, there are 2
    > servings for the FSB, it would require 2 FSB cycles to pick up
    > the data. Similarly when writing.

    No. See above.

    >> No, that's wrong. You're ass-u-ming that the geometry of the processor
    >> and memory buses are the same. In most cases they're not.
    >
    > yeah, I was assuming that, but based on the tables I saw at
    > pcguide.com and scott mueller's article. Collectively they said that
    > Pentiums have 64-bit data buses and DDR RAM (at least PC66-
    > PC4300) has 64-bit memory bus.

    They do.

    > To me, that means that the geometry is the same.

    No. You're forgetting that one is DDR and the other QDR.

    <Snip RH's explanation of P4 and DDR bus geometry>

    > but isn't that a beautiful real world illustration of what I mean.

    Lol, depends what you're talking about, as you've just spent the first half
    of this post claiming that the memory bus runs twice as quick as the
    processor bus, so do you mind telling us exactly what you do mean?

    > In that example, the effective speed of the FSB is 800=4*200.
    > And the effective speed of the memory bus is 400=2*200. It's
    > efficient, because the bandwidth is equal.

    Correct.

    > Although that required the actual speeds to be the same, it means
    > that the FSB's effective speed is half that of the memory bus.

    Eh? You seem to be confusing yourself with all this talk of "effective
    speeds". The Pentium 4 bus's "effective speed" (as you call it) is four
    times faster than the FSB clock, as there are four transfers per clock
    (QDR), so the FSB's effective speed is twice that of the DDR memory bus,
    but, to compensate, a dual channel DDR memory bus is twice as wide as the
    processor's.

    > When you say "If you keep your memory synchronous, you also
    > raise the bandwidth of the memory bus by 33%." You mean
    > keeping the actual memory speed equal to the processor speed,
    > right?

    Yes.

    > The word synchronous is a funny one to use, because SDRAM is
    > always synchronous, that's what the S stands for.

    The "S" in SDRAM is there partly for marketing reasons, partly because it
    refers to the way the memory works inside each DIMM. You need to separate
    the term "Synchronous" (capital S) as it applies to SDRAM memory modules
    from the word "synchronous".

    > If the actual speeds are different, it would stiull be synchronous,

    No. You have to understand that "synchronous" (small s) is just a verb that
    could be used in any scenario. Could even say that my girlfriend's heart is
    synchronous to mine when they start beating together, but that's another
    story. ;-)

    It literally refers to things running at the same speed. In this scenario,
    when I say that the FSB and memory buses are synchronous, it means they're
    running at a 1:1 multiplier. No more or less. If I say the memory and
    processor buses are asynchronous, it means that the multiplier is something
    other than 1:1.

    >> If, OTOH, you keep the FSB the same, but raise the CPU and
    >> memory multipliers by 33%, you get the faster memory and CPU
    >> clocks, but you don't raise the processor bus, so the resulting
    >> bottleneck - assuming that the bandwidths matched in the first
    >> place - will curtail your performance gain.
    >
    > And in your earlier example
    > P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2)
    > - a 2:1 multiplier. There's no bottleneck because the bandwidths of the
    > fsb and memory bus are equal.

    Yep, sure, assuming that the memory was dual channel, the bandwidths would
    match. What I was trying to say though, was that, if you assumed that the
    CPU in the system above was an engineering sample, your "FSB doesn't matter"
    theory would be comprehensively disproved by the following test:

    Test configuration A:
    CPU multiplier: 12x
    FSB: 266MHz
    FSB:Memory bus multiplier: 1:1

    Test configuration B:
    CPU multiplier: 18x
    FSB: 200MHz
    FSB:Memory bus multiplier: 3:4

    In the configurations above, CPU core speed A=CPU core speed B, while memory
    bus speed A=memory bus speed B, give or take any floating point differences.
    However, in configuration A, the processor bus bandwidth would be 8.5GB/sec,
    theoretically matched to the memory bandwidth. In configuration B, the
    processor bus bandwidth would be reduced to 6.4GB/sec, creating the
    bottleneck. Even allowing for inefficiency and latency in the memory bus,
    configuration A should still have a tidy performance advantage, despite,
    processor and memory speeds being the same.

    > yeah, and those calculations i did with the 33% increase all agree
    > with what you're saying.
    >
    > thanks

    No worries. :-)
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  48. Archived from groups: alt.comp.hardware.overclocking (More info?)

    "James Hanley" wrote in message...
    > Course Neither Dual inline nor DDR increase the actual speed.

    You have to be careful with your terminology here, as you're in danger of
    confusing/transposing different factors. In particular it looks like you're
    a little too keen to mix bus speeds and bandwidths.

    > However, DDR is considered to increase the effective speed, even
    > though it does not increase the speed in cycles per second.

    Double data rate increases bandwidth, not speed. ;-)

    > It just writes twice as much per cycle, which has the same effect
    > as working at twice the frequency.

    Correct.

    > according to the table in pcguide.com article "Memory Banks
    > and Package Bit Width", it says Pentiums have a 64-bit data
    > bus.

    Yes, eight bytes/64 bits. I mentioned this in my previous post.

    > So a Pentium with DDR RAM DIMMS has a 64-bit data bus and
    > 64-bit memory bus. If the effective speeds are the same, - for
    > example - the actual FSB is the same, the FSB is dual pumped
    > and so is the memory bus,

    No. The front side bus on the Pentium 4 CPU's is *quad* pumped, so four data
    transfers per clock, not two as you say above.

    > If the memory bus can throw around twice as much data as the
    > FSB, then it is not an efficient set up.

    That comment is incorrect, because your underlying assumption about the P4
    processor bus being double pumped is wrong.

    > It is only efficient if the DDR RAM is half the speed of the FSB.

    See above.

    > Since in one memory bus clock cycle when reading, there are 2
    > servings for the FSB, it would require 2 FSB cycles to pick up
    > the data. Similarly when writing.

    No. See above.

    >> No, that's wrong. You're ass-u-ming that the geometry of the processor
    >> and memory buses are the same. In most cases they're not.
    >
    > yeah, I was assuming that, but based on the tables I saw at
    > pcguide.com and scott mueller's article. Collectively they said that
    > Pentiums have 64-bit data buses and DDR RAM (at least PC66-
    > PC4300) has 64-bit memory bus.

    They do.

    > To me, that means that the geometry is the same.

    No. You're forgetting that one is DDR and the other QDR.

    <Snip RH's explanation of P4 and DDR bus geometry>

    > but isn't that a beautiful real world illustration of what I mean.

    Lol, depends what you're talking about, as you've just spent the first half
    of this post claiming that the memory bus runs twice as quick as the
    processor bus, so do you mind telling us exactly what you do mean?

    > In that example, the effective speed of the FSB is 800=4*200.
    > And the effective speed of the memory bus is 400=2*200. It's
    > efficient, because the bandwidth is equal.

    Correct.

    > Although that required the actual speeds to be the same, it means
    > that the FSB's effective speed is half that of the memory bus.

    Eh? You seem to be confusing yourself with all this talk of "effective
    speeds". The Pentium 4 bus's "effective speed" (as you call it) is four
    times faster than the FSB clock, as there are four transfers per clock
    (QDR), so the FSB's effective speed is twice that of the DDR memory bus,
    but, to compensate, a dual channel DDR memory bus is twice as wide as the
    processor's.

    > When you say "If you keep your memory synchronous, you also
    > raise the bandwidth of the memory bus by 33%." You mean
    > keeping the actual memory speed equal to the processor speed,
    > right?

    Yes.

    > The word synchronous is a funny one to use, because SDRAM is
    > always synchronous, that's what the S stands for.

    The "S" in SDRAM is there partly for marketing reasons, partly because it
    refers to the way the memory works inside each DIMM. You need to separate
    the term "Synchronous" (capital S) as it applies to SDRAM memory modules
    from the word "synchronous".

    > If the actual speeds are different, it would stiull be synchronous,

    No. You have to understand that "synchronous" (small s) is just a verb that
    could be used in any scenario. Could even say that my girlfriend's heart is
    synchronous with mine when they start beating together, but I'd never use
    such a clinical word to describe such a lovely thing. ;-)

    Synchronous literally refers to things running at the same speed. In this
    scenario, when I say that the FSB and memory buses are synchronous, it means
    they're running at a 1:1 multiplier. No more or less. If I say the memory
    and processor buses are asynchronous, it means that the multiplier is
    something other than 1:1.

    >> If, OTOH, you keep the FSB the same, but raise the CPU and
    >> memory multipliers by 33%, you get the faster memory and CPU
    >> clocks, but you don't raise the processor bus, so the resulting
    >> bottleneck - assuming that the bandwidths matched in the first
    >> place - will curtail your performance gain.
    >
    > And in your earlier example
    > P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2)
    > - a 2:1 multiplier. There's no bottleneck because the bandwidths of the
    > fsb and memory bus are equal.

    Yep, sure, assuming that the memory was dual channel, the bandwidths would
    match. What I was trying to say though, was that, if you assumed that the
    CPU in the system above was an engineering sample, your "FSB doesn't matter"
    theory would be comprehensively disproved by the following test:

    Test configuration A:
    CPU multiplier: 12x
    FSB: 266MHz
    FSB:Memory bus multiplier: 1:1

    Test configuration B:
    CPU multiplier: 18x
    FSB: 200MHz
    FSB:Memory bus multiplier: 3:4

    In the configurations above, CPU core speed A=CPU core speed B, while memory
    bus speed A=memory bus speed B, give or take any floating point differences.
    However, in configuration A, the processor bus bandwidth would be 8.5GB/sec,
    theoretically matched to the memory bandwidth. In configuration B, the
    processor bus bandwidth would be reduced to 6.4GB/sec, creating the
    bottleneck. Even allowing for inefficiency and latency in the memory bus,
    configuration A should still have a tidy performance advantage, despite,
    processor and memory speeds being the same.

    > yeah, and those calculations i did with the 33% increase all agree
    > with what you're saying.
    >
    > thanks

    No worries. :-)
    --


    Richard Hopkins
    Cardiff, Wales, United Kingdom
    (replace .nospam with .com in reply address)

    The UK's leading technology reseller www.dabs.com
    Get the most out of your digital photos www.dabsxpose.com
  49. Archived from groups: alt.comp.hardware.overclocking (More info?)

    James Hanley wrote:
    > Richard Hopkins wrote:
    >> James Hanley wrote:
    [...]
    >>> Here's the weird bit that seems very strange though. Dual
    >>> inline memory is not considered to increase the effective
    >>> speed.
    >>
    >> It doesn't increase the speed in cycles per second, but doubles the
    >> effective width of the memory interface. Remember that
    >> bandwidth=width x speed, so if the speed stays the same but the
    >> width doubles, the bandwidth also doubles.
    >
    > well. Course Neither Dual inline nor DDR increase the actual speed.
    > However, DDR is considered to increase the effective speed, even
    > though it does not increase the speed in cycles per second. It just
    > writes twice as much per cycle, which has the same effect as working
    > at twice the frequency.

    Not exactly. A DDR bus is the same as an SDR bus at the same speed but
    double the width (not the same width and double the speed). There's a subtle
    difference, mainly in latency-bound situations.

    [...]

    --
    Michael Brown
    www.emboss.co.nz : OOS/RSI software and more :)
    Add michael@ to emboss.co.nz - My inbox is always open
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