Exuberant Optimism?

[rettihSlluB]

These days, people are getting to excited to the level of almost getting an orgasm when they listen to Intel's propaganda about their new offerings, let's hope this article can cool some of that "excitement"

http://www.penstarsys.com/editor/company/intel/conroe/index.html

 

[mpjesse]

There are several issues with the FSB that Intel has to work around to get the Conroe generation of products to be high performing. For example, while the highest speed on this bus is 266 MHz, only the data bus is quad pumped (giving the 1066 MHz number often bandied about). The address and command busses are still single pumped, so they essentially run at 266 MHz. The bus is also bidirectional, but not full duplex, which means that during any clock the data/address/command streams are traveling in only one direction. Once that is finished the bus switches back the other direction. Data does not simply stream in and out through the FSB, but rather it is a one way street at any one time, and when needed that street travels in the other direction.

While this worked fine for many generations of Pentiums, it is now looking far too creaky and slow to truly feed the new generation of Intel processors. The memory controller that is located on the chipset is running at chipset speed, not CPU speed. So for a 800 MHz FSB processor the memory controller is running at 200 MHz, but for a 1066 MHz FSB product the controller is running at 266 MHz. This is a far cry from AMD’s memory controllers that run from 1.8 GHz to 2.8 GHz.

I agree with his assesment there. Intel's biggest bottleneck is going to become it's FSB and memory controller. The problem intel has is AMD's patent on the onboard memory controller. Intel is going to have to become creative and figure out a way to compete with AMD on this particular point. Intel needs to design a next generation bus that ditches the "quad pumped" design. To date I've not heard of them even talking about this...

-mpjesse

 

[slvr_phoenix]

Intel's biggest bottleneck is going to become it's FSB and memory controller. The problem intel has is AMD's patent on the onboard memory controller. Intel is going to have to become creative and figure out a way to compete with AMD on this particular point. Intel needs to design a next generation bus that ditches the "quad pumped" design. To date I've not heard of them even talking about this...

I think the real question has never been if but when, and with what. Obviously the memory controller that Intel uses won't last forever.

But is it actually a problem now? I mean let's face it, which is by far the largest stream, address, command, or data? Sure the architecture isn't perfect, but for what it's used for? I doubt it's much of a constraint. This would be less true if the prefetch sucked, but all-in-all, as a complete system, I doubt it's much of a problem yet.

And, again, I'm sure that Intel will replace it or upgrade it once it does become a problem. It's just a matter of timing. It probably won't be replaced (or at least upgraded) until it becomes a significant factor.

 

[slvr_phoenix]

These days, people are getting to excited to the level of almost getting an orgasm when they listen to Intel's propaganda about their new offerings

I have to admit that I'm excited, but not about performance. I'm excited about power usage and thermal output. Which is why, right off the bat, I thought the linked article was pretty meaningless, when it starts by saying:

Recently we have been seeing a wash of interviews, articles, and opinions that are all pointing in one direction; Intel will recover the performance crown with their Conroe/Merom/Woodcrest series of chips.

I don't think a single person with a clue has said that. It'll bridge the performance gap fairly well. But take the performance crown? Not bloody likely, at least not until Intel adds another FPU unit.

No, this article really felt more like just another AMD fanboy ranting along. Not that the points weren't in their own way (more or less) valid, but did they have any actual meaning is the question IMHO.

 

[mpjesse]

Yeah, I think all the "interviews, articles, and opinions" are coming straight from Intel.

No one I know in the enthusiast community believes this to be true...

-mpjesse

 

[slvr_phoenix]

Yeah, I think all the "interviews, articles, and opinions" are coming straight from Intel.

No one I know in the enthusiast community believes this to be true...

-mpjesse

I don't think that I've even heard anyone at Intel say that this will make their procs faster than AMDs. They keep talking about performance per watt over there. :lol:

 

[DuxSyagrius]

Is it really that far fetched to say Intel after Conroe may be faster? If I am not mistaken, didnt the 2ghz Core Duo come in right at or just below the X2 3800 in performance here on a Tom's review? I am certain of it as a matter of fact. Granted, the chip will be like $600, but it does have a 667mhz bus.... and there may be a little room for growth in terms of clock speed. I am not worried about it cuz i just bought a X2 3800 cuz I dont think Intel's next gen is good enough to wait for. But who knows? Judging from the performance of the Core duo in comparison to the X2, I think it is possible that Intel COULD take the performance crown again. Do you all remember when ATI had that incredible run from the 9700 Pro to the X800? I was thinking that ATI would always be on top. I personally hope Intel cranks out good chips and better prices other wise AMD could become just as bad as intel with BS.

 

[slvr_phoenix]

Is it really that far fetched to say Intel after Conroe may be faster?

Yes. Yes it is. Mostly it's because of weak FPU performance IMHO. If Intel fixed that, then it's not far fetched at all.

If I am not mistaken, didnt the 2ghz Core Duo come in right at or just below the X2 3800 in performance here on a Tom's review?

Beats me. I stopped reading THG reviews a while back. :lol:

 

[ltcommander_data]

I don't really see Conroe being bandwidth starved at all. At least not to the point of being uncompetitive. Just looking at Yonah, we see a mobile processor running on a 667MHz FSB that can meet the performance of an X2 at the same clock speed.

"But what about the bigger picture? What does our most recent look at the performance of Intel's Core Duo tell us about future Intel desktop performance? We continue to see that the Core Duo can offer, clock for clock, overall performance identical to that of AMD's Athlon 64 X2 - without the use of an on-die memory controller. The only remaining exception at this point appears to be 3D games, where the Athlon 64 X2 continues to do quite well, most likely due to its on-die memory controller."

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2648&p=14

And this is a 667MHz FSB. Conroe will have a 1066MHz FSB with Extreme Editions having a 1333MHz FSB. With so much additional bandwidth available over Yonah, it's doubtful that Conroe or dual processor Woodcrest would be bandwidth starved. Even in a 4-way Woodcrest situation, with 4 processors on 2 1333MHz FSBs each processor would have 667MHz to work with, the same as Yonah. There would be bandwidth restrictions if every processor is going full tilt, but a lot of that would be alleviated by the fact that Woodcrest would have double or more L2 cache than Yonah. Now on 8-way or higher systems I'll admit Woodcrest would definitely be bandwidth restricted although Intel is planning on implementing a 4 FSB design in those situations.

The problem with the FSB design is not so much bandwidth as latency. Even then the relevence in real world situations depends on the circumstance. As mentioned in the Yonah review, FSB latency only hinders the processor in gaming. This actually wsn't so much of an issue for Dothan since its large 2MB with very low 10 cycle L2 cache latency helped buffer the FSB latency. The problem with Yonah was that the new shared cache required new algorithms that introduced latency. The cache was also asleep by default now and required reawakening for use further adding latency. With the cache size being kept the same, meaning a reduction per core, Yonah's performance couldn't help but fall being buffered only by the increased FSB from 533MHz to 667MHz.

Conroe and Woodcrest won't have as many problems. They will at least double the L2 cache bringing the per core amounts in line with Dothan. The latency may also be reduced if Intel removes the power saving features from Yonah. The caches don't need to be asleep by default, but could just be put to sleep when not in use like in Dothan helping to reduce the cache latency. FSB latency will also be reduced when moving to desktop as Yonah and Merom uses a Power Savings optimized FSB. I may be wrong but I thought the mobile FSBs used less lanes, which while keeping average thoroughput the same, reduced burst speeds. Those cut lanes may have just had to due with reduced power requirements though. In any case, with the FSB not needing to sleep most of the time, latency will also be reduced over Yonah. Latency can also be reduced by running synchronous RAM, which is why it was strange that all the reviews I looked at coupled Yonah's 667MHz with 533Mhz RAM. Intel will also be continuing to optimize their northbridge memory controller. The i975 had reduced latencies and improved performance over the i955 so performance gains are possible. Overall latency won't be reduced to match an onboard memory controller, but the gap can be closed.

FSB design could actually be a benefit of Intel's partnership with Apple. Apple's G5s have an FSB even faster than Intel's topping out at 1.35GHz for the 2.7GHz G5. What's interesting is that Apple reaches this speed with only a dual pumped bus. If Intel adds their quad-pumped architecture to it a 2.7GHz FSB will be more than enough to satisfy Intel's needs. Apple's FSB is also bidirectional like HT allowing them to transfer 1.35GHz in each direction at the same time. Co-operation between Apple and Intel will remove the bandwidth constraints of the FSB, and bidirectional support will cut the latency by avoiding the wait for the bus to switch directions. Of course, this would require Intel to swallow their pride and ask Apple for help, but it shouldn't be that hard to do if Apple already did it to ask Intel for help.

And for slvr_phoenix, one of the major focuses of the Merom family architecture was correcting the FPU limitations. All the executions units have been redesigned. The Inquirer believes the new architecture will easily surpass K8 on integer calculations which isn't so hard to believe given the Pentium M's integer performance, and will likely tie on FP calculations. The execution unit count for the Merom family is likely 3 complex (full) ALUs and 2 full FPUs.

A major limitation in Dothan was the fact that only 1 of the 3 decoders could process SSE instructions. This bottleneck was removed from Yonah by allowing all 3 decoders to process SSE instructions. Further improvement was made by extending micro-ops fusion to include SSE. The major bottleneck is actually not FPU numbers but how instructions are processed. Currently on both Dothan and Yonah, the FPU (vector unit) is only 64-bits wide. This means that SSE (4x32 bit) and SSE2 (2x64 bit) instructions can't fit and must be split into 64-bit pieces. This already means performance is cut in half. The problem gets worse when looking at multiplication. While it can be done at full speed for 32-bit SSE instructions, it only runs at half speed for 64-bit SSE2. This means that SSE performance is cut in half and SSE2 performance is as low as a quarter of potential in the 1 FPU that Yonah has.

Merom and family looks to completely alleviate these problems. The FPU will be full speed 128-bit compatible meaning up to 2 times performance increase in SSE and 4 times in SSE2. These units will be fed by 4 full (complex) decoders. The number of ports has also increased from the current 2 although the specific number hasn't been confirmed. The minimum would be 3 universal ports with 2 shared with the FPUs, while 4 universal ports is also likely which would indicate that another ALU has been added. Expanded micro-ops fusion and the addition of macro-ops fusion along with various prefetch techniques will also help ensure the execution units are operating at max efficiency.

 

[DuxSyagrius]

I just finished reading the article and I am very impressed with what AMD plans. if they can squeeze another 10% out of the the chip clock for clock, I would be happy. But not enough to upgrade again. I did think the FP performance on the core duo was nasty. What really shocked me was the video encoding times. The intel solution lagged significantly and this is the last area intel has a leg to stand on. I dont like intel personally, not even the Pentium M. But they do have a few saving graces:
1. Gamers push the envelope on the performance end and CPUs just arent as important anymore. I read a review on high resolution gaming and the FX chips were within a stone's throw of the sempron chips (which I personally like)

2. These new chips wont need all the cooling (although I think they will still be hotter than AMD chips.)

3. The Turion needs a face lift.

4. Dell doesnt sell AMD systems..... YET!

 

[mpjesse]

My head hurts now.

-mpjesse

 

[slvr_phoenix]

My head hurts now.

-mpjesse

Lunch break! :lol: (It's 12:12 here.)

 

[ltcommander_data]

I should have probably put a warning notice at the top about the length although I really didn't know until the end.

Reading the article again, I found their belief that the Winchester to Venice transition yielded a 5-10% performance increase to be exuberant optimism. In actuality Venice only performs on average maybe 1% faster.

http://www.xbitlabs.com/articles/cpu/display/athlon64-venice_14.html

The biggest jump is 3% in 3DMark05 CPU scores. The move to 90nm SOI also didn't yield temperature decreases or power savings over Winchester.

http://www.xbitlabs.com/articles/cpu/display/athlon64-venice_5.html
http://www.xbitlabs.com/articles/cpu/display/athlon64-venice_6.html

The major benefit of Venice was additional clocking room and the correction of compatibility issues with the memory controller and expanded memory support.

 

[sepuko]

Reading the thing you wrote about Intel's FSB issues gives me certain thoughts. Performance between equally rated processors from Intel and AMD don't really have that BIG difference in performance. Although Intel cpus have such a problem with the "one way street"(which sounds stupid to me). So, what to expect when(they will) Intel comes out with similar(to AMD's) memory controller?

 

[mpjesse]

One thing you can say about Intel's FSB design: it's very frikin scalable. AMD's is not... if you want to change the HT bus and memory controller w/ the Athlon 64, you've got to redesign the core!

So hats off to Intel for creating something that's very scalable. But then again, they've always been good at scalability.

-mpjesse

 

[rettihSlluB]

One thing you can say about Intel's FSB design: it's very frikin scalable

Sorry to differ from you mpjesse, but Intel's FSB is NOT scalable.

Itcommander doesn't mentions the point of AMD going to an 333MHz HTT in all his Intel propaganda. The autor of the article I linked before says that with a 333MHZ HTT X 4 implementation will give AMD a 1333MHz of HTT performance. I believe he's just speculating since AMD can go with a 333MHz X 5 implementation giving socket AM2 an effective 1666MHz HTT which in simple terms means lower latency and increased bandwidth, this is far more scalable than any thing Intel has to offer right now and something that not Intel's fastest FSB can match.

Sorry It_Commander, you'll have to try harder, but be careful not to "cum" on your self when you try again.

 

[ltcommander_data]

Yes 333MHz HT will give more bandwidth, but is it really necessary? This is just like the transition from DDR to DDR2. The benefits are mainly theoretical. In the case of the RAM, I really don't believe that single core chips are bandwidth limited by DDR so they won't see much better performance on AM2. The increased latency of the DDR2 may actually hinder them. Dual cores on the other hand will be able to use the bandwidth so its justified in that case.

Similarly the additional bandwidth of HTT really isn't beneficial. The move from 800MHz to 1000MHz yielded no performance increase so its even more unlikely that going to 1333MHz or higher makes any difference.

http://www.xbitlabs.com/articles/cpu/display/athlon64-3800_3.html

With the memory going through its own bus, the activity through HT to the chipset is greatly reduced. The added bandwidth will be beneficial if and when AMD decides to integrate a PCIe controller, but that is likely several years in the future.

The only real benefit that the added HT bandwidth would give is in multiprocessor situations for cache coherancy. I don't know all the details about cache coherancy and NUMA, but it occurs to me that there's only so much bandwidth that cache coherancy needs especially when a cache is only 1MB big.

The information about Apple is speculation on my part, but it seemed like a logical progression and benefit of their partnership. After all, better FSB and processor performance for Intel means better performance for Apple.

However, the fact that Yonah on a 667MHz FSB can match K8 at the same clock speed with the exception of games is not speculation. Neither is the redesign going into Merom's execution units. The limitations have been identified and solutions have been reported by news sites such as the 4 full decoders, increase in ports, additional prefetch techniques, expanded micro-ops fusion, and additional macro-ops fusion. Obviously some of the details are conflicting but the features themselves are confirmed.

 

[rettihSlluB]

In fact, a speedier HTT link will be of great help for dual core processors (not sure about single cores, but who cares about single cores nowadays?)

Please read this article and you'll know what I mean.

Here's a quote:

Again, AMD's HyperTransport is superior to PCI Express, partly due to that system approach, and HyperTransport III enables throughput of up to nearly 50 Gbytes/sec per channel. A theoretical combination of next-generation Quadrics and HyperTransport III could scale such systems to 32,000 CPUs, for example, with excellent, nearly linear, scaling and a low-latency,

And with this I confirm once more that Intel's FSB is not scalable:

The problem for Intel is that it does not have an interconnect with that kind of capability among its current solutions. Obviously, Intel will need to make a decision about what it is going to do.

I love this jewel:

I honestly think it would be better for Intel to adopt HyperTransport, taking the same pragmatic attitude it did when it adopted AMD64.

Here's the rest of the interview if you're interested:

The processor wars Part I, The death of Alpha

The processor wars Part II, The current generation

The processor wars Part III, Waiting for Merom, Conroe and Woodcrest

The processor wars Part V, Intel's Itanium

 

[endyen]

So much selective bs, where to start.

However, the fact that Yonah on a 667MHz FSB can match K8 at the same clock speed with the exception of games is not speculation.

No, it isn't speculation, it's just not true. Jonah took a hit because it has more pipeline stages than dothan.
Yonah on the other hand has fewer stages than conroe, so conroe wont have the same IPC.
As to latency on DDR2 @ 667 an increase of 50% in latency cycles over 400, will still net a 17% reduction in system latency, in time. Since DDR2 modules with latencies of 3,3,3,8 are becoming more available, that looks to be the case.
As to the increase in HTT, from 200 to 333 mhz, while the bandwidth may not be that important, again the advantage would be to wait states.
Since the HTT is doing that many more "pickups" and "dropoffs", the information will arrive at it's destination that much more quickly.
As to the relative truth of Intel's hype, I can only relate to that through history. The only times I remember seeing this kind of hype from Intel was for prescott, and williamette.
The greatest gain I've seen in one swoop from Intel was going fron P4b to P4c. There really was no pre-release hype for that.
That is how Intel works.

 

[ltcommander_data]

I think I read parts of that interview before, but it's a good one. I've read all the parts again and I should warn people that this is another long post.

Based on that quote a faster HT will help dual cores, but the real help is in multiprocessor systems. Again, this goes back to the need for cache coherancy. HT is not used internally between cores so its benefits to dual cores would be its connection to the chipset.

A point I found interesting from Part II, was the fact that the HT and onboard memory controller design is a disadvantage to expansion cards. This is because any main memory access requires a jump from GPU to northbridge and then to the processor memory controller, 2 hops. On an Intel system only 1 hop is required. I pointed this issue out in the summer asking if anyone knew how much of a performance penalty this incurs, and I was immediately jumped on by people for questioning the revolutionary OMC and told I'd be raped, etc. It'd be interesting to see the response now that someone theoretically more respected than myself also brings up this issue.

Since you brought up a quote you liked, I'll bring up some too.

If Conroe appears on schedule, and it has a clock speed of at least 3.0GHz, and I believe the clock speed will be at least 10% above that for top-end parts, we think it will have quite a performance advantage over the current Athlon 64 scaled up to above 3.0GHz, if it is still available at that time.

From Part III.

It seems that they feel that clock for clock, Conroe will have "quite a performance advantage". AMD scaling above 3GHz will require their 65nm process so I hope they are on the ball because Intel already has 3.33GHz Conroe Extreme Editions with a 1333MHz FSB ready to ship to developers.

http://www.theinquirer.net/?article=29031

I really doubt AMD can reliably hit above 3GHz on their current 90nm SOI design since even in Part I of the article it mentions that they can't get the FX-60 above 2.8GHz. This is on air cooling of course.

I ran my dual-core 3.46GHz Presler benchmarking unit at 4.26GHz dual-core, with low heat and full stability, for an hour, while the competing 2.6GHz AMD FX60 could only reach 2.8GHz, cooled in the same way, in stable operation. Over two weeks later, I’m still trying to tune the FX60 system to enable 3.02GHz operation.

It's interesting that in addition to the above mention of Presler, this is the first article I've read that someone actually praises the performance of Intel's slapped together dual cores.

Essentially, Intel simply bolted together two cores for the Intel Extreme Edition Pentium.

Even so, while Intel's solution was architecturally clumsy, it did work, and it turned in record performance. I have tested both solutions, and while AMD has the performance lead in most areas, there are a few areas where Intel maintains the lead.

Even I don't believe the Extreme Edition's give "record performance".

Other good quotes are

By the time Merom, Conroe and Woodcrest have appeared, AMD's performance lead will have evaporated.

My belief is that Intel will regain much of its performance leadership on the desktop and probably also in small servers. And where servers or workstations have a chipset supporting two front-side buses (FSBs) in parallel, as well as a large memory system, the next-generation Woodcrest could come to have the performance leadership for this server segment.

This is an interesting perspective coming from articles that Bullshitter put forward to question Merom and family.

I see endyen's responded now, so I should defend the last two quotes by saying that Nebojsa Novakovic, who made them, is not alone. They are perfectly in line and mirror those from The Inquirer which said that Intel should regain the lead on consumer desktop and 2-way servers, come closer in 4-way, and be completely hopeless in 8-way and above without some bandwidth miracle.

For desktop:
http://www.theinquirer.net/?article=28602

The second half will open with Intel having a minor lead, and it will stretch out during Q4. My, how things change.

For server:
http://www.theinquirer.net/?article=28639

The close of 2006 will see Intel in the lead by a little on most workloads at the 2S 4C level. At the 2S 8C level, if there ends up being a race, AMD will crush Intel, something that will continue at the 4S 8C and get downright abusive at 4S 16C.

And of course in mobile, Intel will be maintaining their lead:
http://www.theinquirer.net/?article=28624

Intel will have the lead, AMD will be a serious player, and the sun will continue to rise in the morning, set in the evening. We hope. Nothing earth shattering here, the battleground is 45nm, things are coasting until then.

 

[theholylancer]

does this guy under stands how k8 uses memory???

<quote>
These will not be sweeping performance gains, but we can expect to see performance increase due to the usage of DDR-2 as well as these other enhancements.
</quote>


DDR2 will not increase performance, if at all it will most likely reduce perf due to their sad timings, their high speed is great for intel with higher FSB requirements for higher GHz but not to intel where GHz does nto matter, but amd memory controller is better with tigher timings.....

 

[ltcommander_data]

I don't really think that Yonah had a longer pipeline than Dothan. Dothan's range was more than the Pentium III's 10 and less than K8's 14. I believe 12 is often indicated as the most reasonable number given the amount of clock speed increases possible over the PIII. Yonah is quoted as being between 12 and less than Conroe's 14. Personally, I think the number remains at 12, but even a 1 stage increase isn't catastrophic especially considering the number of other enhancements like going from 1 full decoder to 3 and expanded micro-ops fusion that increase efficiency.

Any reduction in performance of Yonah over Dothan is largely due to the increased L2 cache latency of 14 cycles compared to the previous 10 cycles. This in turn was due to the cache being asleep by default and needing constant reawakening.

so conroe wont have the same IPC

You're right, Conroe's IPC will be higher.

http://www.theinquirer.net/?article=28602

On the up side, the IPC (instructions per clock) of the Conroe will be about 30 per cent higher than the current Pentium M parts.

You believe Yonah to have lower efficiency than Dothan. Fine, we'll skip Yonah then. Conroe will be 30% higher than Dothan which would therefore put it better than Yonah.

According to The Inquirer's calculations, a 2.66GHz Conroe will be faster than a 3 GHz AM2 X2. Now we can call the calculation speculation, so we'll attach a large margin of error. We already know that Intel has a 3.33GHz Conroe read which is clocked 25% faster than the 2.66GHz and 11% faster than the 3GHz AM2 X2, which should be a large enough margin of error. Speculation is that AMD will be able to release the X2 at around 3.2GHz by the end of the year assuming the 65nm transition goes smoothly. Even then Intel will still maintain a clock speed advantage compared to an efficiency advantage. Since we are concerned about propaganda, it should be noted that those calculations were done by The Inquirer and were not quoted from Intel PR figures. Granted The Inquirer itself may have bias, but at least its not straight from Intel's mouth.

I already posted the 3.33GHz Conroe link before but here it is again for convenience.
http://www.theinquirer.net/?article=29031

I know Intel has a lot of hype, but seeing as Merom has been taped out and in production since June of last year, it isn't far fetched that the family is on or ahead of schedule. This is further reinforced by the fact that Conroe is supposed to launch at 2.67GHz and yet Intel already has 3.33GHz parts available for developers. No matter how Conroe performs against K8 at launch, Intel has already left themselves a lot of room if needed.

 

[jokersgrin]

Damn now my brain is fried :!:
Thinking about this a little while enjoying the pain killers I just took for a slipped disk.
Right now news threads and everyone else is speculating about the next generation or evolution of AMD AM2 and future designs, and how AMD and Intel will fight the game to keep or take market shares. But the truth be known no one really knows what AMD going to put out. And to me it seems Intel is holding out

I remember somthing that AMD did, a partnership with some memory company that had something to do with increaseing the onboard L1 and L2 cache size!
Also read some article about possible new test platform that AMD was messing with. A test platform that(please note I'm on drugs so be gentle) had intigrated the fuctions of a northbridge chipset into the cpu.
Ladies and Gentlemen I think we just might see a whole different ball game comeing soon. Hell half the stuff you people where talking about makes sense. I just think we might see a huge leap here soon from Intel or AMD. Like eveyone here has said the cats ain't outa the bag yet!

 

[Ruby]

A while back I read some interesting things about future Xeon processors and desktop CPU's from Intel. Apparently they plan to adopt Quad-Channel into their setup, and from past speculation I read, it will actually decrease performance. I keep reading about people saying "New Intel CPU's will perform on par or better than AMD", but people are forgetting 1 important thing, AMD isn't sitting idle. I read a excerpt from an individual working at AMD (cannot remember his/her job title) and they stated by the end of this year, they plan to introduce a brand new architecture than what they currently use.

One thing to really look forward to, which I did not know of, is HyperTransport 3. AMD hasn't even fully intro'd HyperTransport 2.0 into current A64's or O64's, being HT2.0 is 1.4GHz x2, I would be thinking the SAM2's and Socket F's would introduce this, as it would be very interesting. I hear mentioned here about performance with DDR2 and AMD, I read that AMD plans to be able to run DDR2-667 at 3-3-3-8 timings, which is a standard value-RAM PC3200 speed, and much lower than current DDR2. Obviously AMD can't control RAM timings, but I'm sure they're working with partners to make it happen.

Really interesting is going to be these 2 brands in the next 12-18 months as they introduce their new CPU's into Desktop & Server variations, regardless of who of them wins, the consumer, us, always wins. One thing I didn't like of what I heard, I believe I heard right, was that increased clock speed of AMD HyperTransport doesn't increase bandwidth, but I find different. Even OC'ing my 3700+ by 15-20MHz yielded a 200-300MB/s more memory bandwidth, which is nothing to shun off. If this is how the new 333MHz bus will be, with respectable timings, there is no reason to not believe DDR2 will be a great addition to AMD's already great lineup of Processors.

I also read about Intel developing their own Onboard-Memory Controller, but from what the article at the beginning of this thread stated, that would be inflicting on AMD's patent, which is interesting. I do believe that too much hype is being thrown at new things, especially CPU's and GPU's, but GPU's is for another thread. What it really will come down to is waiting, waiting to see the real-world performance of these CPU's and to see if any bottlenecks are taken care of and how efficient these CPU's will be. But I believe the biggest thing needing help is Software. No point having a Quad-Core CPU if every program you run is Single-Threaded (Not saying there is no Multi-Threaded applications) , kinda pointless (Unless you do UnGod Multi-Tasking).

I guess we'll just have to wait and see, the less hype there is the better, at least IMHO.

Peace...

 

[ltcommander_data]

AMD has plans to use Z-RAM which may be integrated into their 65nm processors later. It's still debatable whether it'll be fast enough to be used in the L2 cache however. An L3 cache implementation looks more likely. The target size is currently 5MB. This really isn't that impressive though considering Intel desktop chips already have 4MB of L2 cache, and Woodcrest will have 16MB. This is on 65nm. Intel has already produced fully functional SRAM on 45nm which will help increase cache sizes further. In any case, extremely large caches would be more beneficial in a server environment than desktop.

AMD is also planning on integrating a PCIe controller into their processors. Intel on the other hand has already demoed a processor with a northbridge and voltage regulator integrated.

http://www.anandtech.com/tradeshows/showdoc.aspx?i=2511

Integrated northbridges are unlikely to come to fruitation though since their isn't sufficient flexibility. Intel would have to produce some processors with integrated graphics, some without, w/wo dual channel support, etc which is just too complicated.