AM2 FX LINE TO UP CACHE
More good news about AMD's offerings.
This might be AMD's first attempt to use Z-RAM for their L3 cache.
Quote:The next gen of AMD FX chips will have the full 'big cache' Opteron level of L3 cache, most likely 4MB
This might be AMD's first attempt to use Z-RAM for their L3 cache.
You know, I can't help but think that AMD needing to use L3 cache is hilarious. We've always heard people praising AMD's OMC and the extra bandwidth and reduced latency it provides, and talk about Intel struggling and having to use huge L2 caches to catch up with AMD. Now we see AMD having to introduce L3 cache "to keep up with the competition". Quite the change indeed. I guess that's why the FX TDP has increased to 125W.
Quote:You know, I can't help but think that AMD needing to use L3 cache is hilarious. We've always heard people praising AMD's OMC and the extra bandwidth and reduced latency it provides, and talk about Intel struggling and having to use huge L2 caches to catch up with AMD. Now we see AMD having to introduce L3 cache "to keep up with the competition". Quite the change indeed. I guess that's why the FX TDP has increased to 125W.
Don't make your self an @sshole with that statement.
The reason why AMD is implementing a shared L3 cache in the FX line is for sake of improving virtualization and multitasking.
A L3 cache in some "sort" of way will help off-load the L2 cache. The new AM2 processors and socket F are far from being bandwidth-starved (can't say the same for Intel). Anyhow, AMD can't stay at 2MB of L2 cache for all their lives. Intel on the other hand has to increase their cache to 4-6-8 and (if I'm not wrong) 16MB of L2 cache. They've being doing this with every processor revision. This is still sign that their FSB approach is not helping them at all. That's why they needed 65nm faster than AMD for them to fit all those huges caches and help them "a little" with power consumption.
Anyhow, The FX at 2.8GHz, dual channel DDR2"-800 and 4MB L3 cache will give Intel's Conroe a pain in the @ss. Conroe will be a lackluster just like Yonah was. (IMHO)8)
Warning: Long post. This is a culmination of several pieces from things I've previously written so I hope it flows properly.Quote:Anyhow, The FX at 2.8GHz, dual channel DDR2"-800 and 4MB L3 cache will give Intel's Conroe a pain in the @ss.
What you are doing is actually assuming L3 cache will actually bring a sizable performance increase. You are correct that AM2 processors are far from bandwidth-starved. The advantage of the OMC implementation has always been the low latencies which keep the memory a lot closer to the processor. However, in order for the L3 cache to actually help offload the L2 cache, the latency needs to be very low, as comparable to the L2 cache's latency as possible. Z-RAM is already known to be unable to maintain L2 type latencies. With the latencies of the L3 cache, you really aren’t going to see much benefit from it since going to RAM won’t take much longer. If AMD processors don’t see much benefit going from 512k to 1MB of L2 cache, L3 cache is even less likely to make a difference.
Even discounting the OMC, the lack of benefit to AMD using large caches is evident by analysing their cache architecture.
Many people assume that increasing the caches automatically means greater performance. In fact, this is only true in some circumstances. AMD’s architecture especially doesn’t see large performance increases with larger L2 and L3 cache. AMD uses an exclusive cache architecture which puts a lot of focus on the size of the L1 cache. The size of the other caches are less important and increasing them don’t result in much performance benefit.
The makers of CPU-Z have a great section on cache architectures in their K8 analysis.
http://www.cpuid.com/reviews/K8/index.phpQuote:AMD made the choice of an exclusive relationship for the first time on the Thunderbird. The CPU architecture fits on this choice, with a big L1 cache and a 8-entries victim buffer.
This choice allowed AMD to build CPUs with a L2 cache size from 64 to 512KB with the same core, and even the Duron that has a 64KB L2 cache provides very good performance. In another hand, the increase of the L2 size does not provide a big jump in performance.
Intel on the other hand, uses an inclusive cache architecture which puts the emphasis on L2 cache size. The difference between inclusive and exclusive caches is why Intel always has a smaller L1 cache than AMD, simply because it isn’t as important for them. However, increases in L2 cache size creates more noticeable performance benefits on Intel’s inclusive cache.
The summary is here:Quote:The exclusive relationship is the most flexible, as it allows lot of different configurations in keeping a good performance index. The drawback is that the performance does not increase very much with the L2 size. The inclusive relationship can only be chosen for performance purpose, knowing for example that increasing the L2 will create a performance boost.
I am not going to judge which design is better, because they are both valid solutions to the same problem each with their own advantages and disadvantages. However, this is also why I take offence to people blindly criticizing Intel using large caches. Of course they use them, because they are designed for them and benefit from them. You can hardly make it sound disgraceful for Intel to use large L2 caches, when that is the advantage of the inclusive cache design. The ability for large caches to relieve the FSB is just a double benefit. Even if Intel used an OMC, they would still have large caches because they work for them.
The flaw in large caches is of course the increased transistor count. However, Intel has always been able to leverage their manufacturing strengths by making rapid process transitions. If the large caches made Intel processors phenomenally more expensive than their AMD counterparts then obviously Intel has a major problem with the inclusive approach. However, Intel is able to keep costs down. Even now, Intel is planning major price cuts, up to 50% on its dual core processors making the cost of its approach a non-issue.
For interest, the two disadvantages of the inclusive cache architecture that CPUID mentions are the need to maintain the right ratio between the L1 and L2 cache sizes and the smaller total cache size due to the L1 being duplicated in the L2 cache. The first disadvantage was the reason why the Northwood Celerons performed so poorly, because they were very constrained by their tiny L2 cache. Given the performance of the Pentium M and the large size of the L2 cache in current processors, Intel has found the correct ratio between the L1 and L2 cache size. (The ratio was mainly the bigger the L2 cache the better anyways). Even the 256k L2 cache on the Prescott Celeron Ds were a huge improvement. The second concern about reduction in total cache size due to duplication is no longer a concern, because the L2 cache size has grown to such a size that the kB that is wasted by duplicating the L1 cache is irrelevent. In any case, both disadvantages of inclusive cache that CPUID mentions are now moot.
As well, the article from The Inquirer doesn’t give any time frame for the addition of L3 cache. The FX-62 won’t have it. I seriously doubt that AMD will be able to integrate 4MB of additional cache economically using the 90nm process, so it’ll have to wait for 65nm. This would put introduction at the end of this year at the earliest or possibly the beginning of 2007.
Very well said.
I also want to point out 9-inch stated that Intel needed to resort to a 65nm design because they need so much room on the die for such a large cache. While this maybe somewhat true although I find it rather baseless as no one article or anyone has ever mentioned it before, Intel has really gone to this process so they can concentrate on producing quad cores. Quad cores is not really possible on 90nm.
Besides, if you want to argue about cache sizes, than explain to me why AMD wants to increase their cache sizes on their chips. Perhaps to follow in Intels footsteps? Also, they are switching to higher DDR2 that of which Intels currently use. I see a pattern here.