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DRAM Command Rate Explained

Last response: in Memory
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February 23, 2006 3:25:24 AM

I moved this and renamed it, maybe it will get more attention :p .

It seems as though nobody here knew what 1T and 2T command rates really were, we knew the performance drop, but not what it really is, at least I thought. Well, I found a website that wrote an article back in 2001, and it told me what that was. Basically, the command rate is the time it takes for the initial memory fetch to occur. Let me explain:

When the MC (Memory Controller) first tries to access memory, it has to latch onto a memory bank, known as CS (Chip Select). Then it proceeds to find the column (CAS), the Row (RAS), and then return the data to the CPU. Now, 1T means it takes 1 clock cycle to "find" a memory bank, vs. 2T where it takes 2 clock cycles to "find" the memory bank. But there's a sorta quirk, this only happens the first time data is attempted to be fetched from memory, and all subsequent accesses to that chip are done w/o delay, making the command rate null after the initial chip fetch.

"Whether the chip select can be executed in a single clock or whether it needs two clocks, depends on a variety of factors. Among the most crucial contributing factors appears to be the number of banks populated within the system from which the correct bank has to be selected. In a single bank configuration, the system already knows that all data have to be within this bank. If more banks are populated, there is an additional decision involved. Translated, that means that the number of chips within the entire pool of system memory plays an important role in how fast the DRAM command can be executed. This is highly oversimplified but to spell it out, it means that a single DIMM with only 8 chips (single bank) is easier and faster decoded within the entire possible memory space than 2 DIMMs with 2 banks each.

Other factors involve the distance of the DIMM slot from the memory controller and, most importantly, the quality of the DIMM's PCB. If a 4-layer PCB with its relatively high noise level is used, there is a fat chance of ever hitting a 1t command rate. A 6 layer PCB on the other hand has a better signal to noise ratio and can greatly speed up the decoding (on the level of the PCB). It is, therefore, not surprising that, even if the same chips are used on different DIMMs, the differences in the PCB will dictate whether the module is able to perform at a command rate of 1T or 2T
"

So in a nutshell, just with having to raise latencies such as CAS, RAS, etc. when overclocking to remain stable, you should raise the command rate as well. Now, I know that this may be old or may not of been needed, but I actually never knew and I know a few people on here didn't, if you find it helpful, good, if you didn't, well, something to read .

~~Mad Mod Mike, pimpin' the world 1 rig at a time
February 23, 2006 4:11:49 AM

Hence the term "Command Per Clock" in my piece of shit Ultra-D's bios.
April 18, 2009 4:07:08 PM

Very helpful, thanks!! Exactly the information I was looking for.
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April 2, 2010 6:25:54 PM

Four years after the initial post, I still really appreciate the information! It helps a lot! :) 

Thanks.
May 7, 2011 9:38:43 AM

This is very important. I got bsod when the command rate is set to 1 T. Need 2 T.
May 16, 2011 5:16:41 AM

This is the first time I heard of DRAM Command Rate. Glad to learn it here.



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Leo
Website: How to Make Money Online Resources
June 18, 2014 4:01:23 PM

Eight years later, thanks! :D 
a c 139 } Memory
June 18, 2014 6:58:30 PM

Eggz said:
Eight years later, thanks! :D 


Too bad it's really just a load of hogwash.

Cmd Rate is the number of rising edges that must be present between the assertion of the Chip Select commend and the first Row Active command. In a 1T configuration the RA command can occur on the cycle immediately following CS. In a 2T configuration, a no-op must be inserted for one cycle (the CS assertion is held as is, as a DRAM no-op is defined as CS asserted and RAS/CAS/WE unasserted). In a 3T configuration, two no-ops must be inserted.
June 18, 2014 7:39:16 PM

Pinhedd said:
Cmd Rate is the number of rising edges that must be present between the assertion of the Chip Select commend and the first Row Active command. In a 1T configuration the RA command can occur on the cycle immediately following CS. In a 2T configuration, a no-op must be inserted for one cycle (the CS assertion is held as is, as a DRAM no-op is defined as CS asserted and RAS/CAS/WE unasserted). In a 3T configuration, two no-ops must be inserted.


This sounds like the same thing as above in different phrasing. Both seem to say that first cycle, second cycle, and third cycle are 1T, 2T, and 3T, respectively; although, my motherboard only accepts 1 and 2 as an input. Either way, the bottom line seemed to be that lower is better.

Another useful thing to know would be how to know which setting to use without trial and error. Is it in the XMP profile or do we just have to do stability testing to see what works best? If we have to test, it doesn't seem worth changing from "Auto" given how small of an impact there is. I couldn't tell any significant difference, or any at all for that matter.

The main reason I was looking into Command Rate was because it's a field in the same group of settings as where the UEFI prompts me to input the XMP profile numbers for my memory modules. The sticks survive stability testing at the profiled settings of 9-11-11-28 with a Command Rate of 1, but 2 and Auto also work just the same.
!