The PCIe link is built around a bidirectional, serial (1-bit), point-to-point connection known as a "lane". This is in sharp contrast to the PCI connection, which is a bus-based system where all the devices share the same unidirectional, 32-bit, parallel bus.
At the electrical level, each lane utilizes two unidirectional low voltage differential signaling (LVDS) pairs at 2.5 gigabaud. Transmit and receive are separate differential-pairs, for a total of 4 data wires per lane.
A connection between any two PCIe devices is known as a "link", and is built up from a collection of 1 or more lanes. All devices must minimally support single-lane (x1) links. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for very good compatibility in two ways. A PCIe card will physically fit (and work correctly) in any slot that is at least as large as it is (e.g. an x1 card will work in an x4 or x16 slot), and a slot of a large physical size (e.g. x16) can be wired electrically with fewer lanes (e.g. x1 or x8; however it must still provide the power and ground connections required by the larger physical slot size). In both cases, the PCIe link will negotiate the highest mutually supported number of lanes. It is not, however, possible for a device to operate in a slot that is physically smaller than it (eg. a x4 card cannot fit in a slot which is physically an x1 slot - though it could operate in a x4 slot wired with only 1 lane).