AMD has better position to go 'nano'

[Whizzard9992]

I personally like Intel, but AMD is best poised at this point to produce the next-gen nano based processors. We'll see what happens, but here's my take:

The simplest nano technogy that's closest to production is carbon nano tubing. The nano technology allows a very large amount of RAM to be placed on a very small die. The ram is much faster, requires much less voltage, and produces less heat.

Ultimately, it's very possible that we can see the RAM and processor being on the same die. With AMD's on-die memory controller, they're already half-way there.

If AMD has even a 1-year head start with this, they would crush intel. It's RAM at speeds comperable to cache.

 

[psyno]

Er.. but you haven't said why you think AMD is in a position to capitalize on this...

And anyway, why do you think RAM would be moved to the chip instead of used to increase the amount of RAM available in the current general arrangement?

 

[MadModMike]

I personally like Intel, but AMD is best poised at this point to produce the next-gen nano based processors. We'll see what happens, but here's my take:

The simplest nano technogy that's closest to production is carbon nano tubing. The nano technology allows a very large amount of RAM to be placed on a very small die. The ram is much faster, requires much less voltage, and produces less heat.

Ultimately, it's very possible that we can see the RAM and processor being on the same die. With AMD's on-die memory controller, they're already half-way there.

If AMD has even a 1-year head start with this, they would crush intel. It's RAM at speeds comperable to cache.

Getting to a slightly different topic...sorta...

AMD is set to roll out many new technologies in 2007, such as HyperTransport 3.0, AMD64 FPU Extensions, FB-DIMM RAM, DDR3, Rambus (maybe) so it looks like AMD is set to take back the throne that Conroe will take by a small margin. I don't believe Conroe will be 20% faster as Intel states, simply because when it comes down to it, the Memory Bandwidth on both systems will now be the same, with the Conroe Architecture being slightly better, thus giving it the slight edge of IMHO 5-12%, at best. Really, all Conroe is gonna do, is level the playing field and pit CPU vs. CPU intstead of DDR2 vs. DDR1.

PS: Don't forget about K10's!

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[Whizzard9992]

Sorry:

AMD is in the better position because as it stands now, moving the memory on-chip is a matter of removing the external FSB. (Oversimplified, I know) The memory controller is already on the chip.

For Intel, they need to move the memory controller on the chip AND remove the external FSB. As easy as it sounds, they have a large product line that's built on the current 'northbridge' FSB architecture.

Removing the FSB decreases the cost (and size) of motherboards. It also removes a LOT of pins from the chip, further reducing costs. It also would greatly increase the performance of memory by reducing latency and errors. The FSB could be increased to higher frequencies because there isn't so much of a capactitance concern as with running trails.

 

[MadModMike]

Sorry:

AMD is in the better position because as it stands now, moving the memory on-chip is a matter of removing the external FSB. (Oversimplified, I know) The memory controller is already on the chip.

For Intel, they need to move the memory controller on the chip AND remove the external FSB. As easy as it sounds, they have a large product line that's built on the current 'northbridge' FSB architecture.

Removing the FSB decreases the cost (and size) of motherboards. It also removes a LOT of pins from the chip, further reducing costs. It also would greatly increase the performance of memory by reducing latency and errors. The FSB could be increased to higher frequencies because there isn't so much of a capactitance concern as with running trails.

Careful what you call "On-Chip", an Intel fanboy had to correct me by saying "On-Chip is the NB, On-Die is in the CPU", and yes, he is a dumbass for saying that.

Topic: Removing the FSB will bring HELL alot more pins to the CPU, because now the CPU is required to have all the interconnects to the Memory, which is why AMD has 939 Pins in the CPU for Dual Channel (although over 250 are unused pins).

I already proposed this, they need to do away with the NB completely and integrate everything into the CPU directly, such as the case (maybe) with new Opteorn 64's where the PCI-E, PCI-X, and RAM are integrated, into the CPU. Easier way would be to just have AMD use their own Chipsets (AMD 8xxx Series) and create 1 or 2 I/O Hubs and connect everything to them, than use HyperTransport 8-Bit Full Duplex @ 600MHz, that would do away with alot of latency and provide best performance, IMHO.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[enewmen]

MMM:

About what quarter do you see the new AMD technologies in 2007 (rough guess).
HyperTransport 3.0, AMD64 FPU Extensions, FB-DIMM RAM, DDR3, etc.

I am very interested about this. I think a lot of this and the K10 will come together.

"I have yet to see any nano tube memory actually work" 100 Gig on a SD card will be the holy grail.

 

[MadModMike]

MMM:

About what quarter do you see the new AMD technologies in 2007 (rough guess).
HyperTransport 3.0, AMD64 FPU Extensions, FB-DIMM RAM, DDR3, etc.

I am very interested about this. I think a lot of this and the K10 will come together.

"I have yet to see any nano tube memory actually work" 100 Gig on a SD card will be the holy grail.

Going on purely an educated guesstimate, I would submise seeing HyperTransport 3.0 in H1 (Half 1) 2007, and the rest following in H2 (Half 2) 2007.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[dvdpiddy]

oh yeah and don't forget pd-soi and z-ram see z-ram needs soi to function so intel cant use it hah

 

[Whizzard9992]

Topic: Removing the FSB will bring HELL alot more pins to the CPU, because now the CPU is required to have all the interconnects to the Memory, which is why AMD has 939 Pins in the CPU for Dual Channel (although over 250 are unused pins).

*confused* How will removing the FSB add more pins to the CPU? It should remove the pins required for the FSB (Unless they make RAM expandable externally. Let's not assume that for sake of argument). I'm saying if the RAM is always stored on-die (), there would be no need for the extra pins. In fact, CNT RAM requires so little voltage that you probably wouldn't need that many voltage refs or decoupling caps.

 

[Whizzard9992]

[quote="prozac26]Agree, AMD has a good architecture in place already, so they need to work towards improving it. Intel needs a whole new architecture to compete with AMD's architecture. 20% is way off, I think Conroe will be very competitive with AM2, but AMD can now work on on newer things since their architecture is mainly in place.[/quote]

I personally see Conroe taking the throne for a short while in terms of perfomance (I'll **** myself if Intel somehow takes Performance-Per-Watt). I think we're on the verge of great leaps in technology, and it's those companies that are best poised for those leaps when they arrive that will take dominate. This is historically the case with any business.

 

[MadModMike]

Topic: Removing the FSB will bring HELL alot more pins to the CPU, because now the CPU is required to have all the interconnects to the Memory, which is why AMD has 939 Pins in the CPU for Dual Channel (although over 250 are unused pins).

*confused* How will removing the FSB add more pins to the CPU? It should remove the pins required for the FSB (Unless they make RAM expandable externally. Let's not assume that for sake of argument). I'm saying if the RAM is always stored on-die (), there would be no need for the extra pins. In fact, CNT RAM requires so little voltage that you probably wouldn't need that many voltage refs or decoupling caps.

If you're talking about doing away with the Memory Controller all together and having On-Die Memory, that is just stupid. 1: Put's memory manufacturers out of business. 2: HUGE latencies and ENORMOUS size on the Die of the CPU (Going to need 2GB+ for this year and next). I will admit, I do not know much about CNT RAM (as I believe it to be just another attempt at "revolutionizing computers".) so I don't know how it is or how well it scales, but I don't see integrated memory happening anytime soon.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[Whizzard9992]

If you're talking about doing away with the Memory Controller all together and having On-Die Memory, that is just stupid. 1: Put's memory manufacturers out of business. 2: HUGE latencies and ENORMOUS size on the Die of the CPU (Going to need 2GB+ for this year and next). I will admit, I do not know much about CNT RAM (as I believe it to be just another attempt at "revolutionizing computers".) so I don't know how it is or how well it scales, but I don't see integrated memory happening anytime soon.

I wouldn't call it stupid...

CNT RAM promises to have the capability of providing > 5GB of RAM in the same amount of space the cache currently takes (The actually estimate 1/2 terabyte at tech peak, but that seems a little optimistic). Because the information doesn't need to be constantly refreshed it also takes MUCH less voltage. The increase in die size will be easily offset by the smaller manufacturing process (32nm and 45 nm easily by the time CNT comes out in full force). The latency will be much less. You still need a memory controller; it just doesn't have worry about communicating externally. This translates to lower latency and higher bandwidth because clock rates wouldn't be constricted by transmission methods.

As for putting memory mfr's out of business, I don't think desktop processor architecture would do that. I doubt servers would use on-die RAM. And I doubt that if AMD had the option of doing this and crushing Intel, they'd say, "Well, maybe we shouldn't for the sake of the Memory Mfrs".

 

[enewmen]

I will still rather see a 100 gig "flash" type card first.
I heard one is in the making, but I have not seen anything solid yet,

 

[psyno]

There is no way that main memory is going to be integrated onto the chip!

First, supposing it could fit, it destroys the modularity of current systems.

We could build a system today where the entirety of main memory of an i286 class system could fit on the chip. Yet we don't. Can you guess why?

We don't want the same amount of memory, only in a physically smaller package. We want more memory in the same size package. What I mean is, who cares if you can fit a terabyte of RAM on a chip if you could fit a petabyte in an off-chip arrangement?

Finally, carbon nanotube may be very small compared to traditional capacitors, but guess how they're read and written? With components no smaller than existing technology. Combine that with the current naive approach to manufacturing them, and that memory isn't fitting anywhere special any time soon.

 

[joset]

...but AMD is best poised at this point to produce the next-gen nano based processors. We'll see what happens, but here's my take:

The simplest nano technogy that's closest to production is carbon nano tubing. The nano technology allows a very large amount of RAM to be placed on a very small die. The ram is much faster, requires much less voltage, and produces less heat.

Ultimately, it's very possible that we can see the RAM and processor being on the same die. With AMD's on-die memory controller, they're already half-way there.

1. CNT is nowhere near mass-production, yet;

2. Although there are specialized companies in CNT R&D, Intel and IBM (to name just two), are way ahead of AMD in nanotechnologies R&D (sometimes, size DOES count, in these matters);

3. The "3D Core Stacking Processor" concept, was first put forward by Intel, a few years ago (which included memory, ASICs & DSPs...);

4. CNT is a technological quantum jump: it's not just "memory made of" but everything, silicon/non-silicon wise, in computing...;

5. Both AMD & Intel (again, to only mention two), would have to redo the entire microarchitecture of their processors (unless AMD only replaced their on-die memory-controller(s) with CNT, which isn't what you're referring to... and even if... you may deduce the rest);

6. Probably, AMD will use Innovative Silicon's Z-RAM on-die (replacing both L1/L2 SRAM caches); that'll be a major achievement in the high-speed/density memory market & will give - certainly - a huge boost in reducing ON-DIE memory latency & power consumption;

7. IBM & Infineon (among others) have already developed a high-speed/density memory, the "Magnetoresistive RAM", MRAM; of what it will be made, only time will tell;

8. Intel's FSB is a parallel bus, which also connects to system memory; AMD uses the System Request Interface & a Crossbar Switch to link to system memory. As MadModMike already pointed out, the pinout would not be decreased, unless ALL system RAM was to be... on-die, as you said. That will result in, at least, two unsurmountable issues: if on-chip stacked memory, the number of vertical vias would be huge (connecting to the cores); if on-die, even with [very] high density nanoscale memory technologies (like CNT), a two or four GB of on-die L3 would result in a chip with an area (or volume!) of... you know...


Cheers!

 

[Whizzard9992]

Wow. I'm amazed at how wrong you both are. Please do your research before trying to flame someone. I also want to note that I'm just 'thinking out loud', and simply stating that CNT will make on-die RAM possible, and if it happens then AMD is in the best position to execute that kind of move. Allow me to correct you:

1. CNT is nowhere near mass-production, yet;

2007 is far, far away I guess

2. Although there are specialized companies in CNT R&D, Intel and IBM (to name just two), are way ahead of AMD in nanotechnologies R&D (sometimes, size DOES count, in these matters);

There are a LOT of small companies whose technologies are up for sale/licensing. AMD has plenty of money to jump on the bandwagon. They have a LOT vested into nano technology, as I'm sure actual research will reveal.

3. The "3D Core Stacking Processor" concept, was first put forward by Intel, a few years ago (which included memory, ASICs & DSPs...);

So if Intel thought it was a good idea, but scrapped it because it was too expensive, then why do you also say that it's never going to happen...? Obviously SOMEONE at Intel thought it was a good idea.

4. CNT is a technological quantum jump: it's not just "memory made of" but everything, silicon/non-silicon wise, in computing...;

Not sure what this means, exactly, but CNT is not a quantum leap. They're making CNT RAM on silicon in labs today.

5. Both AMD & Intel (again, to only mention two), would have to redo the entire microarchitecture of their processors (unless AMD only replaced their on-die memory-controller(s) with CNT, which isn't what you're referring to... and even if... you may deduce the rest);

I'm referring to moving the entire RAM onto the chip. WOrk will be onvolved, but AMD will have less work than intel.

6. Probably, AMD will use Innovative Silicon's Z-RAM on-die (replacing both L1/L2 SRAM caches); that'll be a major achievement in the high-speed/density memory market & will give - certainly - a huge boost in reducing ON-DIE memory latency & power consumption;

Not sure what this has to do with the OP...

7. IBM & Infineon (among others) have already developed a high-speed/density memory, the "Magnetoresistive RAM", MRAM; of what it will be made, only time will tell;

MRAM has an access rate of 15ms and suffers from the same problems as hard drives in terms of storage limitations and volitility. CNT RAM is much better.

8. Intel's FSB is a parallel bus, which also connects to system memory; AMD uses the System Request Interface & a Crossbar Switch to link to system memory. As MadModMike already pointed out, the pinout would not be decreased, unless ALL system RAM was to be... on-die, as you said. That will result in, at least, two unsurmountable issues: if on-chip stacked memory, the number of vertical vias would be huge (connecting to the cores); if on-die, even with [very] high density nanoscale memory technologies (like CNT), a two or four GB of on-die L3 would result in a chip with an area (or volume!) of... you know...

... did you do ANY research before making this post? Did you even read all the posts? With CNT you can easily put 2GB in less space than cache currently takes. Even if it was as large as a RAM chip is currently, you're still talking about easily fitting this in a chip package with a processor at 45 nm.

 

[Whizzard9992]

What I mean is, who cares if you can fit a terabyte of RAM on a chip if you could fit a petabyte in an off-chip arrangement?

Why do video card makers put memory on the video card instead of using the AGP bus to use system memory? Oh yeah... it's faster.

Finally, carbon nanotube may be very small compared to traditional capacitors, but guess how they're read and written? With components no smaller than existing technology. Combine that with the current naive approach to manufacturing them, and that memory isn't fitting anywhere special any time soon.

Um, you don't know anything about CNT, do you? CNT's don't replace capacitors lol. They're more like transistors with static "On-Off" states that only require voltage to change, not maintain. CNT RAM (by nantero) is manufactured using existing lithographic systems: the same systems that make AMD's SOI and Intel's 65nm. They're read and written in areas much smaller than current transistors.

 

[MadModMike]

Even if CNT RAM is set to "revolutionize" computers, how much do you think a standard Dual-Core CPU with 1GB of On-Die NRAM (the name for CNT RAM) is going to cost? Not saying it may cost the manufaturers alot or a little, but you think they're going to pass them savings onto the consumers? Try no. Likley to Not cost $400, add a few 0's to the end and that's what they're going to market it for.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[psyno]

What I mean is, who cares if you can fit a terabyte of RAM on a chip if you could fit a petabyte in an off-chip arrangement?

Why do video card makers put memory on the video card instead of using the AGP bus to use system memory? Oh yeah... it's faster....

Are you serious? Video cards are another example of the same CPU->Caches->off-chip RAM heirarchy being successful in the same way. The RAM is not integrated into the chip on a video card either (and won't be). This has nothing to do with the point you quoted.

...manufactured using existing lithographic systems...

They're read and written in areas much smaller than current transistors.

Notice any problem there? Currently the interface between the nanotubes and traditional circuitry is still large and thus still limits density.

Um, you don't know anything about CNT, do you? CNT's don't replace capacitors lol. They're more like transistors with static "On-Off" states that only require voltage to change, not maintain.

Sigh. Capcitors serve the function of saving state in traditional DRAM. Carbon nanotubes serve the function of saving state in carbon nanotube RAM. Therefore, carbon nanotubes functionally replace capacitors. Thanks for you idiotic explanation of how carbon nanotubes are applied though.

NRAM (the name for CNT RAM)

(It's actually just the name for Nantero's implementation). Agreed though!

 

[Whizzard9992]

NRAM is nantero's name for CNT RAM. They're the big name player for now, but not the big player. We'll see if the name sticks.

It's still purely speculative, but I doubt that if AMD had the opportunity to steal a large market share from Intel that they'd price themselves out. The nice thing about Nantero's NRAM is that it works on Silicon, so it can be implemented with minor changes to the manufacturing process.

 

[Whizzard9992]

Are you serious? Video cards are another example of the same CPU->Caches->off-chip RAM heirarchy being successful in the same way. The RAM is not integrated into the chip on a video card either (and won't be). This has nothing to do with the point you quoted.

I'm referring to your original question: why would you use a local GB of RAM if you can access a remote TB of RAM, and the answer is speed. A Video card is a good example of having a local repository of RAM when a much larger repository is available.

...manufactured using existing lithographic systems...

They're read and written in areas much smaller than current transistors.

Notice any problem there? Currently the interface between the nanotubes and traditional circuitry is still large and thus still limits density.
? Silicon transistors are made up of layers and are larger than a single gap of crossed CNT. There's no gap limiting this technology. It's meant to be a bridge to allow CNT to work with existing manufacturing processes.

Sigh. Capcitors serve the function of saving state in traditional DRAM. Carbon nanotubes serve the function of saving state in carbon nanotube RAM. Therefore, carbon nanotubes functionally replace capacitors. Thanks for you idiotic explanation of how carbon nanotubes are applied though.

I know how regular RAM works. It actually works with Caps AND transistors for each cell, so a CNT bridge replaces each CELL if you really want to get technical. Your original statement was that CNT components are no smaller than existing components, which is false, and that the approach to manufactuing them is naive, which I'm sure your expertise in nanotechnology can support.

 

[Caboose-1]

You guys are pretty quick to call each other idiots. If you KNOW FOR A FACT that someone has their information wrong, then you should help them fix it politely. Calling someone an idiot only relsults in the same coming from "the idiot." Insulting someone is all too common especially when you know the person your insulting cannot get to you. Its getting rediculous, this is what drives knowledgeable help away from those you actually need it.

 

[psyno]

I'm referring to your original question: why would you use a local GB of RAM if you can access a remote TB of RAM, and the answer is speed. A Video card is a good example of having a local repository of RAM when a much larger repository is available.

And a video card is a good example of having only a tiny amount of memory available on the chip while going off chip to get to much more memory, i.e. the current scheme used by current CPUs.

? Silicon transistors are made up of layers and are larger than a single gap of crossed CNT. There's no gap limiting this technology. It's meant to be a bridge to allow CNT to work with existing manufacturing processes.

This is actually my point. This means that the density (bits/area, not tubes/area) of memory currently reachable is limited by the lithography.

Your original statement was that CNT components are no smaller than existing components, which is false,

(as above)

and that the approach to manufactuing them is naive, which I'm sure your expertise in nanotechnology can support.

It is naive. It is a first hack at getting something working. When the technology matures, it won't be done in the same way. I said what I meant.

 

[9-inch]

AMD is set to roll out many new technologies in 2007, such as HyperTransport 3.0, AMD64 FPU Extensions, FB-DIMM RAM, DDR3, Rambus (maybe) so it looks like AMD is set to take back the throne that Conroe will take by a small margin. I don't believe Conroe will be 20% faster as Intel states, simply because when it comes down to it, the Memory Bandwidth on both systems will now be the same, with the Conroe Architecture being slightly better, thus giving it the slight edge of IMHO 5-12%, at best. Really, all Conroe is gonna do, is level the playing field and pit CPU vs. CPU intstead of DDR2 vs. DDR1.

I really have a problem believing Intel's propaganda about their upcoming offerings delivering 20% more performance than AMD's processors. Maybe, they were referring to current processors and not the upcoming AM2 ones, since AMD said that with their new process they can achieve 25% on 90nm and 40% on 65nm (not my words, it's AMD and IBM claims). If so, then Intel's claim about 20% performace gains over current Athlons will be nothing compared to the upcoming AM2 processors.

As I said before, Conroe will be a lackluster just the way Jonah did.

 

[Whizzard9992]

I really have a problem believing Intel's propaganda about their upcoming offerings delivering 20% more performance than AMD's processors.

If Intel is wrong, you'll see a lot of Intel fanboys jumping off of bridges.

I'm writing my will now

I personally like Intel's products, but AMD is american, so I'm rooting for the home team. I'd like to see them crush Intel, but I don't jump ship so easily.