AMD SHOWS OFF THREE NEW SOCKETS AT SPRING IDF

[9-inch]

According to that article, AMD's next architecture will see the light of day sometime next year.

If you’re expecting something earth shattering from AMD or finally some specifications for their 2007 CPU lineup, you’ll have to wait longer. AMD tells us that after Socket-AM2 and its mobile/server variants are launched then they will begin talking about their new architectures.

AMD did a great job to make socket S1 (754 pins) dual channel.

The Turion 64 X2 will be using AMD’s new Socket-S1, the mobile version of Socket-AM2. The 754-pin mobile Socket-S1 has a dual channel DDR2 interface like the 940-pin desktop AM2 socket. You may be wondering how AMD was able to cram more than twice the data pins in a 754-pin package as they did with the original Socket-754 Athlon 64s, the answer is that the first generation of AMD’s Athlon 64 was a bit over-designed for its needs. We’ve heard that around 10% of the pins on the original Athlon 64s were unnecessary, so with some tweaking it’s not too far fetched to see a dual channel memory controller implemented in the same number of pins.

Read the whole thing here:
http://www.anandtech.com/tradeshows/showdoc.aspx?i=2710

 

[MadModMike]

According to that article, AMD's next architecture will see the light of day sometime next year.
If you’re expecting something earth shattering from AMD or finally some specifications for their 2007 CPU lineup, you’ll have to wait longer. AMD tells us that after Socket-AM2 and its mobile/server variants are launched then they will begin talking about their new architectures.

AMD did a great job to make socket S1 (754 pins) dual channel.

The Turion 64 X2 will be using AMD’s new Socket-S1, the mobile version of Socket-AM2. The 754-pin mobile Socket-S1 has a dual channel DDR2 interface like the 940-pin desktop AM2 socket. You may be wondering how AMD was able to cram more than twice the data pins in a 754-pin package as they did with the original Socket-754 Athlon 64s, the answer is that the first generation of AMD’s Athlon 64 was a bit over-designed for its needs. We’ve heard that around 10% of the pins on the original Athlon 64s were unnecessary, so with some tweaking it’s not too far fetched to see a dual channel memory controller implemented in the same number of pins.

Read the whole thing here:
http://www.anandtech.com/tradeshows/showdoc.aspx?i=2710

Looks like Socket S1 changed from 638 pins to 754, that's interesting.

~~Mad Mod Mike, pimpin' the world 1 rig at a time